Tarachand Pagarani 4ec5c21d4c fix CI issues		2021-12-17 04:46:56 -08:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	add example of setting bistream for hard logic block from eblif	2021-12-14 07:05:15 -08:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	add example of setting bistream for hard logic block from eblif	2021-12-14 07:05:15 -08:00
openfpga_arch	add example of setting bistream for hard logic block from eblif	2021-12-14 07:05:15 -08:00
openfpga_cell_library	[HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected	2021-10-30 11:45:01 -07:00
openfpga_shell_scripts	fix CI issues	2021-12-17 04:46:56 -08:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_yosys_techlib	fix CI issues	2021-12-17 04:46:56 -08:00
regression_test_scripts	re-enable counter_5clock,sdc_controller, lut_adder tests	2021-11-19 18:06:06 +05:30
scripts	Adding Yosys+Verific support.	2021-10-29 18:34:27 +05:00
tasks	fix CI issues	2021-12-17 04:46:56 -08:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Change arch for Sapone test	2021-10-30 15:23:19 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00