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add example of setting bistream for hard logic block from eblif

This commit is contained in:
Tarachand Pagarani 2021-12-14 07:05:15 -08:00
parent 08f6b9637d
commit 31f47a44af
9 changed files with 75 additions and 6 deletions
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27
openfpga_flow/benchmarks/micro_benchmark/mult/mult_16/mult_16.v Normal file
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@ -0,0 +1,27 @@
//-------------------------------------------------------
// Functionality: A 8-bit multiply circuit using macro
// Author: Tarachand Pagarani
//-------------------------------------------------------
module mult16(a, b, out);
parameter DATA_WIDTH = 16; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b;
output [2*DATA_WIDTH - 1 : 0] out;
(* keep *)
mult_16 #(.MODE(1'b0)) DSP (
.A(a),
.B(b),
.Y(out),
);
endmodule

27
openfpga_flow/benchmarks/micro_benchmark/mult/mult_8/mult_8.v Normal file
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@ -0,0 +1,27 @@
//-------------------------------------------------------
// Functionality: A 8-bit multiply circuit using macro
// Author: Tarachand Pagarani
//-------------------------------------------------------
module mult8(a, b, out);
parameter DATA_WIDTH = 8; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b;
output [2*DATA_WIDTH - 1 : 0] out;
(* keep *)
mult_8 #(.MODE(1'b1)) DSP (
.A(a),
.B(b),
.Y(out),
);
endmodule

2
openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
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@ -94,4 +94,4 @@ stat
# Output netlists
#########################
opt_clean -purge
write_blif ${OUTPUT_BLIF}
write_blif -param ${OUTPUT_BLIF}

1
openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
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@ -1,6 +1,7 @@
# Yosys synthesis script for ${TOP_MODULE}
# Read verilog files
${READ_VERILOG_FILE}
read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
# Technology mapping
hierarchy -top ${TOP_MODULE}

2
openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -286,7 +286,7 @@
<pb_type name="mult_16" physical_mode_name="mult_16x16"/>
<!-- Bind the primitive pb_type in the physical mode to a circuit model -->
<pb_type name="mult_16[mult_16x16].mult_16x16_slice.mult_16x16" circuit_model_name="frac_mult_16x16" mode_bits="0"/>
<pb_type name="mult_16[mult_8x8].mult_8x8_slice.mult_8x8" physical_pb_type_name="mult_16[mult_16x16].mult_16x16_slice.mult_16x16" mode_bits="1" physical_pb_type_index_factor="0">
<pb_type name="mult_16[mult_8x8].mult_8x8_slice.mult_8x8" physical_pb_type_name="mult_16[mult_16x16].mult_16x16_slice.mult_16x16" mode_bits="0" physical_pb_type_index_factor="0">
<port name="A" physical_mode_port="A[0:7]" physical_mode_port_rotate_offset="8"/>
<port name="B" physical_mode_port="B[0:7]" physical_mode_port_rotate_offset="8"/>
<port name="Y" physical_mode_port="Y[0:15]" physical_mode_port_rotate_offset="16"/>

7
openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga
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@ -1,6 +1,6 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --constant_net_method route
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --constant_net_method route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT}
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
@ -8,6 +8,9 @@ read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
# Read OpenFPGA simulation settings
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Read OpenFPGA bitstream settings
read_openfpga_bitstream_setting -f ${OPENFPGA_BITSTREAM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --sort_gsb_chan_node_in_edges
@ -43,7 +46,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
write_fabric_bitstream --file fabric_bitstream.bit --format xml
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist

3
openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v
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@ -8,7 +8,7 @@ module mult_8(
);
assign Y = A * B;
parameter MODE = 1'b1;
endmodule
//-----------------------------
@ -22,4 +22,5 @@ module mult_16(
assign Y = A * B;
parameter MODE = 1'b0;
endmodule

4
openfpga_flow/tasks/fpga_verilog/dsp/multi_mode_mult_16x16/config/bitstream_annotation.xml Normal file
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@ -0,0 +1,4 @@
<openfpga_bitstream_setting>
<pb_type name="mult_16[mult_16x16].mult_16x16_slice.mult_16x16" source="eblif" content=".param MODE" is_mode_select_bitstream="true"/>
<pb_type name="mult_16[mult_8x8].mult_8x8_slice.mult_8x8" source="eblif" content=".param MODE" is_mode_select_bitstream="true"/>
</openfpga_bitstream_setting>

8
openfpga_flow/tasks/fpga_verilog/dsp/multi_mode_mult_16x16/config/task.conf
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@ -19,12 +19,14 @@ fpga_flow=yosys_vpr
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_verilog/dsp/multi_mode_mult_16x16/config/bitstream_annotation.xml
# Yosys script parameters
yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v
yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v
yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
# VPR parameter
openfpga_vpr_device_layout=3x4
openfpga_vpr_circuit_format=eblif
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm.xml
@ -34,6 +36,8 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_12/mac_12.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_16/mac_16.v
bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult_8/mult_8.v
bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult_16/mult_16.v
[SYNTHESIS_PARAM]
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
@ -43,7 +47,9 @@ bench0_top = mac_4
bench1_top = mac_8
bench2_top = mac_12
bench3_top = mac_16
bench4_top = mult8
bench5_top = mult16
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
#end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=