Commit Graph

19 Commits

Author SHA1 Message Date
tangxifan 1f38e17111 bug fix for naming conflicts in mux local encoder and architecture decoders 2020-07-03 14:12:13 -06:00
tangxifan 0a3c746fb1 now split CB module bus ports into lower/upper parts 2020-07-01 14:37:13 -06:00
tangxifan 2e7684b746 adapt bus ports in connection block module builder 2020-06-30 17:50:53 -06:00
tangxifan 2ef083c49d adapt SB module builder to use bus ports 2020-06-30 16:02:40 -06:00
tangxifan 675a59ecb8 Move fpga_bitstream to the libopenfpga library and add XML reader 2020-06-20 18:25:17 -06:00
tangxifan 0bee70bee6 finish memory bank configuration protocol support. 2020-06-11 19:31:13 -06:00
tangxifan 0e16ee1030 add configuration bus nets for memory bank decoders at top module 2020-06-11 19:31:13 -06:00
tangxifan fbe05963e0 add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol) 2020-06-11 19:31:12 -06:00
tangxifan 65df309419 bug fixing for frame-based configuration protocol and rename some naming function to be generic 2020-06-11 19:31:10 -06:00
tangxifan 290dd1a8a6 add frame decoder builder to all the module graph builder except the top-level 2020-06-11 19:31:09 -06:00
tangxifan 8864920460 add frame-based memory module builder 2020-06-11 19:31:09 -06:00
tangxifan 8695c5ee78 add options to use general-purpose wildcards in SDC generator 2020-06-11 19:31:02 -06:00
tangxifan 68b7991a46 bug fixed for sdc on memory blocks 2020-04-21 13:37:56 -06:00
tangxifan bcb86801fa bug fixed in gpio naming for module manager ports 2020-04-05 17:26:44 -06:00
tangxifan 37423729ec bug fixing for naming the duplicated pins 2020-03-07 15:44:57 -07:00
tangxifan 7fcd27e000 now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer 2020-03-03 12:29:58 -07:00
tangxifan e37ac8a098 add grid module Verilog writer 2020-02-16 16:04:41 -07:00
tangxifan 072965cd64 make grid module builder online; basic support on physical tiles 2020-02-13 15:27:16 -07:00
tangxifan f11832b8cf start integrating module graph builder 2020-02-12 17:53:23 -07:00