tangxifan
|
2666726f36
|
[Script] Remove clock routing from example openfpga shell script without ace
|
2021-04-16 20:46:49 -06:00 |
|
tangxifan
|
23d08757cf
|
[Script] Add example script without using ACE2
|
2021-04-16 20:20:10 -06:00 |
|
tangxifan
|
bbdc0e53af
|
[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures
|
2021-04-16 20:14:48 -06:00 |
|
tangxifan
|
b11d03f9c5
|
[Test] Deploy new test to CI
|
2021-04-16 20:01:40 -06:00 |
|
tangxifan
|
93be81abe1
|
[Test] Add test case for architecture using DFF with reset
|
2021-04-16 20:00:48 -06:00 |
|
tangxifan
|
5414a6a3da
|
[Script] Add yosys script with custom DFF tech mapping
|
2021-04-16 20:00:30 -06:00 |
|
tangxifan
|
4239bb4e68
|
[Arch] Patch architecture files using multi-mode DFFs
|
2021-04-16 19:59:55 -06:00 |
|
tangxifan
|
f2f7f010ea
|
[Arch] Add new architectures using DFF with reset in VPR
|
2021-04-16 19:26:18 -06:00 |
|
tangxifan
|
64294ae4eb
|
[Doc] Update README for architecture files due to new architecture features
|
2021-04-16 19:25:54 -06:00 |
|
tangxifan
|
71df9700ea
|
Merge pull request #290 from lnis-uofu/iwls2005
[WIP] Add opencore RTLs from IWLS 2005 benchmarks
|
2021-04-16 17:41:05 -06:00 |
|
tangxifan
|
ff4460695b
|
[HDL] Add dff tech map files for yosys
|
2021-04-16 17:00:55 -06:00 |
|
tangxifan
|
e46c6e75a3
|
[Benchmark] Add missing RTL for IWLS2005 benchmarks
|
2021-04-16 16:50:41 -06:00 |
|
tangxifan
|
f395ed2718
|
[Test] Deploy iwls tests to CI
|
2021-04-16 16:13:46 -06:00 |
|
tangxifan
|
87587bbb74
|
[Test] Add iwls2005 benchmarks to regression tests
|
2021-04-16 16:12:05 -06:00 |
|
tangxifan
|
1566a5558a
|
[Test] Add task configuration file for iwls2005
|
2021-04-16 16:10:31 -06:00 |
|
tangxifan
|
43bf016576
|
[Script] Add example openfpga shell script for iwls benchmark
|
2021-04-16 16:09:47 -06:00 |
|
tangxifan
|
26d3b5a954
|
[Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches
|
2021-04-16 16:08:58 -06:00 |
|
tangxifan
|
86ad572530
|
[Benchmark] Add opencore RTLs from IWLS 2005 benchmarks
|
2021-04-16 14:27:54 -06:00 |
bbleaptrot
|
410c6a12ff
|
Update figures to be more accurate and clean
|
2021-04-16 11:46:12 -06:00 |
|
bbleaptrot
|
221822f0f0
|
update figures to correctly display out ports
|
2021-04-16 11:33:01 -06:00 |
|
bbleaptrot
|
423d814730
|
Update to include new figures
|
2021-04-13 16:04:20 -06:00 |
|
bbleaptrot
|
eff784e77b
|
Upload new figures for spypad tutorial
|
2021-04-13 15:53:51 -06:00 |
|
bbleaptrot
|
46f60d0704
|
Provide more explanation in Pre-Built Spypads
|
2021-04-12 18:10:36 -06:00 |
|
bbleaptrot
|
0606479bf8
|
Edit figures to better fit page
|
2021-04-12 17:53:31 -06:00 |
|
bbleaptrot
|
bb5cd1de47
|
Update to fix :numref: error example figure
|
2021-04-12 17:09:16 -06:00 |
|
bbleaptrot
|
a0b01dccc7
|
Update spypads_tutorial.rst to address comments
Add links to github OpenFPGA architecture files, reference fig_gpout_ports, instead of emphasize lines switch to numbering the important lines
|
2021-04-12 17:02:56 -06:00 |
|
bbleaptrot
|
64e8e623a5
|
Update to fix links to proper syntax
|
2021-04-12 16:14:00 -06:00 |
|
bbleaptrot
|
bad49cdb75
|
Update to change Spypads to spypads
|
2021-04-12 16:07:38 -06:00 |
|
bbleaptrot
|
1744ce594e
|
Rename Spypads_tutorial.rst to spypads_tutorial.rst
|
2021-04-12 16:06:44 -06:00 |
|
tangxifan
|
6dea269018
|
Merge branch 'master' into tutorials
|
2021-04-12 15:10:25 -06:00 |
|
bbleaptrot
|
90df365259
|
Fix a spacing issue on line 250
|
2021-04-12 14:21:53 -06:00 |
|
bbleaptrot
|
198882da89
|
Update link to From Verilog to Verification
|
2021-04-12 14:20:40 -06:00 |
|
bbleaptrot
|
b176ca6c0c
|
Update to improve readability
|
2021-04-12 14:13:41 -06:00 |
|
bbleaptrot
|
a2c2b634e6
|
Update link for _user_defined_template.v
This ensures it goes to the correct page after pull request 274 no longer works
|
2021-04-12 14:00:54 -06:00 |
|
bbleaptrot
|
f626b17d04
|
Update user_defined_temp_tutorial
Change "example" in the beginning of the page to "tutorial" for clarity
|
2021-04-12 13:58:19 -06:00 |
|
tangxifan
|
0cfea2f73c
|
Merge pull request #287 from lnis-uofu/fpga_sdc_test
Enriched FPGA-SDC regression tests by sweeping time units
|
2021-04-11 21:52:20 -06:00 |
|
tangxifan
|
b469705819
|
Merge branch 'master' into fpga_sdc_test
|
2021-04-11 21:14:46 -06:00 |
|
tangxifan
|
1db8bd7eec
|
[Test] Update regression test with new SDC tests
|
2021-04-11 20:24:32 -06:00 |
|
tangxifan
|
07f6066c11
|
[Script] Update timing unit in SDC example script
|
2021-04-11 20:24:18 -06:00 |
|
tangxifan
|
94c4c817eb
|
[Test] Expand sdc time unit test to sweep all the available units
|
2021-04-11 20:14:09 -06:00 |
|
tangxifan
|
c9f27ec4c2
|
Merge pull request #286 from lnis-uofu/generate_testbench_test
Update generate_fabric and generate_testbench test cases
|
2021-04-11 18:05:20 -06:00 |
|
tangxifan
|
a4893e27cf
|
[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
|
2021-04-11 17:26:27 -06:00 |
|
tangxifan
|
9b7001bc0f
|
Merge branch 'master' into tutorials
|
2021-04-10 17:16:09 -06:00 |
|
tangxifan
|
b4c03bce49
|
Merge pull request #285 from lnis-uofu/fabric_bitstream_writer
Fabric bitstream writer supports multiple regions
|
2021-04-10 16:41:38 -06:00 |
|
tangxifan
|
e5b47b7d3d
|
[Doc] Update documentation on the changes on fabric bitstream file formats
|
2021-04-10 15:45:39 -06:00 |
|
tangxifan
|
7c6e000be8
|
[Tool] bug fix
|
2021-04-10 15:36:02 -06:00 |
|
tangxifan
|
03b68a1fdd
|
[Tool] Reworked fabric bitstream XML writer to consider multiple configuration regions
|
2021-04-10 15:25:39 -06:00 |
|
tangxifan
|
934918d9c0
|
[Tool] Reworked fabric bitstream output file in plain text format; Support multiple regions
|
2021-04-10 15:06:53 -06:00 |
|
tangxifan
|
4b8f5f294a
|
[Tool] Capsulate fabric bitstream organization for configuration chain
|
2021-04-10 14:28:31 -06:00 |
|
tangxifan
|
afa0e751da
|
[Tool] Use alias for complex bitstream data types
|
2021-04-10 14:12:02 -06:00 |