tangxifan
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f102e84497
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[Tool] Add bitstream setting file to openfpga library
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2021-02-01 17:43:46 -07:00 |
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tangxifan
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4b77a3a574
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[Tool] Now activity file is not a manadatory input of openfpga tools
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2021-01-29 11:33:40 -07:00 |
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tangxifan
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dcb50e4f19
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[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
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tangxifan
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81171a8f97
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start transplanting FPGA-SPICE
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2020-07-05 12:10:12 -06:00 |
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tangxifan
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4a2f6dfae2
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add read/write simulation setting commands to openfpga shell
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2020-06-11 19:31:15 -06:00 |
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tangxifan
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4a0e1cd908
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add fabric bitstream data structure and deploy it to Verilog testbench generation
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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8864920460
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add frame-based memory module builder
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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e811f8bb21
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plug in netlist manager and now the include_netlist appears in one unique file
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2020-04-23 20:42:11 -06:00 |
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tangxifan
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037c7e5c43
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adapt top-level function for analysis SDC writer
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2020-03-02 17:58:44 -07:00 |
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tangxifan
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7b18f7cd09
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now the auto select number of clocks in simulation is online
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2020-02-29 13:29:16 -07:00 |
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tangxifan
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25e0583636
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |
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tangxifan
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a26d31b87f
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make write bitstream online
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2020-02-26 11:09:23 -07:00 |
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tangxifan
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8e9660b816
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add mapped block fast look-up as placement annotation
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2020-02-24 16:09:29 -07:00 |
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tangxifan
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2d17395e13
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start integrating fpga_bitstream. Bring data structures online
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2020-02-22 23:04:42 -07:00 |
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tangxifan
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62e4f14e30
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add lb_rr_graph to device annotation
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2020-02-17 17:26:27 -07:00 |
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tangxifan
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6c69b52ded
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Add missing file
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2020-02-17 17:11:29 -07:00 |
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tangxifan
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8b0df8632c
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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tangxifan
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213c611c0b
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add tile direct builder
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2020-02-14 22:21:32 -07:00 |
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tangxifan
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f11832b8cf
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start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |
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tangxifan
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c78d3e9af1
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add mux library builder
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2020-02-12 14:58:23 -07:00 |
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tangxifan
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a31d6c6d1e
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rename pb_type annotation to device annotation
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2020-02-12 09:52:18 -07:00 |
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tangxifan
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1372f748f1
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put GSB builder online
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2020-02-11 16:37:14 -07:00 |
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tangxifan
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dad204674b
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done an initial version of clustering net fix-up based on routing results. Debugging on the way
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2020-02-05 21:50:52 -07:00 |
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tangxifan
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2dc4c26257
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add naming fix-up
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2020-01-29 17:49:33 -07:00 |
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tangxifan
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a6fbbce33e
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start developing the openfpga arch binding to vpr
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2020-01-27 15:31:12 -07:00 |
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tangxifan
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cdb3b6de46
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add read_openfpga_arch to OpenFPGA shell
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2020-01-23 19:10:53 -07:00 |
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tangxifan
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ba207ee5a5
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start split workload from the main.cpp in openfpga
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2020-01-23 13:24:35 -07:00 |