tangxifan
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c08c136844
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set a working range for the encoders
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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386bddacd1
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updated bitstream generator for local encoders
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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557b1af633
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add Verilog generation for local encoders, bitstream upgrade TODO
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2019-08-06 14:17:56 -06:00 |
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tangxifan
|
003883b13b
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implementing the local encoders
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2019-08-06 14:17:55 -06:00 |
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tangxifan
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fb2ca66ce9
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start adding submodules of local encoders to multiplexer
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2019-08-06 14:17:55 -06:00 |
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tangxifan
|
33f3a991b5
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init effort to start developing mux local encoders
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2019-08-06 14:17:55 -06:00 |
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tangxifan
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7748340314
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hot fix on tutorial
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2019-08-06 14:17:55 -06:00 |
Baudouin Chauviere
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0a5546e43c
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Fully functional
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2019-08-05 14:06:07 -06:00 |
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tangxifan
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2291c52fab
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-30 16:54:55 -06:00 |
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tangxifan
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8a046394f8
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add documentation for multi-mode configurable block support
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2019-07-30 16:47:41 -06:00 |
AurelienUoU
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40b7f1cc53
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-07-29 11:45:23 -06:00 |
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tangxifan
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c95fea268d
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Merge pull request #25 from LNIS-Projects/dev
Dev
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2019-07-27 15:20:53 -06:00 |
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tangxifan
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716c3c63c3
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-27 15:06:06 -06:00 |
|
AurelienUoU
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7d469d8b4f
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Docker try 2
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2019-07-22 13:06:46 -06:00 |
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AurelienUoU
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52b754f9c1
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Update
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2019-07-22 10:14:03 -06:00 |
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AurelienUoU
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0854161a63
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Docker update
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2019-07-22 09:42:31 -06:00 |
|
AurelienUoU
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64a67dceaf
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Merge branch 'documentation' of https://github.com/LNIS-Projects/OpenFPGA into documentation
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2019-07-18 16:34:47 -06:00 |
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AurelienUoU
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f4e999ef6d
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Correct error in demo, set a new generated ff_${benchmark}.v file rather than overwrite
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2019-07-18 16:33:23 -06:00 |
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tangxifan
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73d6d5264a
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-18 13:40:19 -06:00 |
|
tangxifan
|
434c0d9683
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hot fix on tutorial
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2019-07-18 13:39:47 -06:00 |
|
tangxifan
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e52deac6ad
|
Merge pull request #20 from LNIS-Projects/dev
Add fracturable LUT documentation
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2019-07-18 09:06:32 -04:00 |
|
tangxifan
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ac1c5bb59a
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Merge pull request #16 from LNIS-Projects/egiacomin-patch-2
Update building.md
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2019-07-17 18:49:11 -04:00 |
|
Xifan Tang
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173440ffc3
|
retry
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2019-07-17 18:46:54 -04:00 |
|
Xifan Tang
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8226f42d3d
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use hfill to place image inline
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2019-07-17 18:46:14 -04:00 |
|
Xifan Tang
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a80199057d
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logo placement
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2019-07-17 18:43:17 -04:00 |
|
Xifan Tang
|
37abd8af40
|
try to place inline logo
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2019-07-17 18:40:26 -04:00 |
|
Xifan Tang
|
f3ed949c4b
|
retry placing images
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2019-07-17 18:36:49 -04:00 |
|
Xifan Tang
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b104de0263
|
resize logo again
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2019-07-17 17:56:06 -04:00 |
|
Xifan Tang
|
b850610cea
|
resize logo to fit
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2019-07-17 17:55:10 -04:00 |
|
Xifan Tang
|
17308621bd
|
resize logo on README
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2019-07-17 17:53:36 -04:00 |
|
Xifan Tang
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af335dff66
|
Merge branch 'documentation' of https://github.com/LNIS-Projects/OpenFPGA into documentation
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2019-07-17 17:51:45 -04:00 |
|
Xifan Tang
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afd78604c9
|
Merge branch 'dev' into documentation: resolved conflicts and add logo files
|
2019-07-17 17:50:11 -04:00 |
|
Xifan Tang
|
6af0d277a2
|
hot fix on fpga logo
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2019-07-17 17:48:01 -04:00 |
|
Xifan Tang
|
5bec11bd6e
|
try to add logo
|
2019-07-17 17:46:25 -04:00 |
|
Xifan Tang
|
e7b40f06b0
|
Add documentation for fracturable LUTs
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2019-07-17 15:21:07 -04:00 |
|
tangxifan
|
8a92a3b589
|
Merge pull request #19 from LNIS-Projects/egiacomin-patch-5
Update how2use.md
|
2019-07-17 14:34:23 -04:00 |
egiacomin
|
922e40131f
|
Update how2use.md
|
2019-07-17 12:33:15 -06:00 |
|
tangxifan
|
a16dae6d8c
|
Merge pull request #18 from LNIS-Projects/egiacomin-patch-4
Egiacomin patch 4
|
2019-07-17 14:33:12 -04:00 |
|
AurelienUoU
|
5947818761
|
Typo correction
|
2019-07-17 12:23:06 -06:00 |
|
egiacomin
|
1da04b9c3a
|
Update tutorial_index.md
|
2019-07-17 12:19:57 -06:00 |
|
egiacomin
|
95b56f31d7
|
Update README.md
|
2019-07-17 12:11:38 -06:00 |
|
egiacomin
|
68c459482f
|
Update building.md
|
2019-07-17 12:09:59 -06:00 |
|
egiacomin
|
f10bce826a
|
Update README.md
|
2019-07-17 12:07:40 -06:00 |
|
egiacomin
|
77e1480a4c
|
Merge pull request #14 from LNIS-Projects/dev
Dev - Critical bug fixing and add support for MUX2 standard cell mapping
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2019-07-17 11:55:52 -06:00 |
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tangxifan
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32e3a556b9
|
bug fixing herited from explicit mapping
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2019-07-17 09:26:05 -06:00 |
|
tangxifan
|
8b8e18a8de
|
bug fixing for mux subckt names
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2019-07-17 08:59:57 -06:00 |
|
tangxifan
|
a2505ff16a
|
turn on std cell explicit port map
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2019-07-17 08:36:09 -06:00 |
|
tangxifan
|
dcc96bf7f5
|
bug fixing
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2019-07-17 08:25:52 -06:00 |
|
tangxifan
|
6e1d49d74e
|
start to support direct mapping to MUX2 standard cells
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2019-07-17 07:54:23 -06:00 |
|
AurelienUoU
|
8b7f20f1ba
|
Merge branch 'dev' into documentation
|
2019-07-17 07:33:30 -06:00 |