AurelienUoU
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ffdcd4bb9c
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Path correction 2
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2019-05-28 11:59:09 -06:00 |
tangxifan
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c75ffa858b
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-28 11:26:16 -06:00 |
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tangxifan
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6f30d3ad05
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support rotation on segment groups inside RRChan and improve rotatable mirror searching
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2019-05-28 11:25:16 -06:00 |
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AurelienUoU
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20f80a73e7
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Correct path to tech files
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2019-05-28 11:24:03 -06:00 |
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AurelienUoU
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e0717369e1
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Re-insert power option in regression test
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2019-05-28 09:48:03 -06:00 |
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tangxifan
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0f5666ea11
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fixed the bug in mirror node direction
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2019-05-27 21:58:21 -06:00 |
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tangxifan
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eece161d58
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keep debugging on Switch Block rotation
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2019-05-27 21:10:30 -06:00 |
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tangxifan
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5720217cfd
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Add copy constructor for RRChan, RRSwitchBlock etc.
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2019-05-27 15:44:34 -06:00 |
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tangxifan
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1bea9870fc
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developed new rotating methods for RRSwitchBlocks, debugging ongoing
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2019-05-26 23:35:30 -06:00 |
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tangxifan
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4b852afeac
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skip rotating mirror detection which is too time-consuming
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2019-05-25 23:41:46 -06:00 |
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tangxifan
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22e71f5847
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Add rotate one side of switch block functionality
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2019-05-25 22:48:07 -06:00 |
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tangxifan
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858a323228
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Add more support for rotating Switch Blocks
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2019-05-25 21:26:35 -06:00 |
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tangxifan
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2eab0b1c1c
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update unique_mirror search algorithm for Switch Blocks
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2019-05-25 19:54:15 -06:00 |
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tangxifan
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d3eae80e64
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implemented an native way in finding rotable Switch blocks
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2019-05-25 19:37:18 -06:00 |
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tangxifan
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ae0248fbc6
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debugging SwitchBlock rotating
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2019-05-24 23:10:30 -06:00 |
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tangxifan
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9adc2945c8
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add rotate functionality for RRSwitchBlock
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2019-05-24 21:40:16 -06:00 |
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tangxifan
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02b48d036d
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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tangxifan
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2c46da6888
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clean-up warnings Verilog routing generator
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2019-05-24 16:29:17 -06:00 |
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tangxifan
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27b996337a
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fixed a critical bug in Compact Verilog generation for SB/CBs
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2019-05-24 16:14:46 -06:00 |
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tangxifan
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1ade1f1d3f
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update SDC generator disabled_unused_mux by using RRSwitchBlock
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2019-05-24 15:42:00 -06:00 |
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tangxifan
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f27b88db8d
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Use RRChan in SDC generator to replace old data structures
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2019-05-24 15:34:56 -06:00 |
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tangxifan
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27c234711e
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clean up warnings in SDC pb_type generator
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2019-05-24 15:23:38 -06:00 |
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tangxifan
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924136e7a2
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Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info
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2019-05-24 15:10:08 -06:00 |
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tangxifan
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994b90ae53
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updated report_timing for using RRSwitchBlock
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2019-05-24 14:25:51 -06:00 |
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tangxifan
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eef1312325
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updated bitstream to use new RRSwitchBlock as well as the report timing engine
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2019-05-24 12:54:10 -06:00 |
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tangxifan
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5de38f023c
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-23 21:53:16 -06:00 |
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tangxifan
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8f4f590ff9
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update Verilog compact_netlist outputter with RRSwitchBlock classes
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2019-05-23 21:52:12 -06:00 |
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AurelienUoU
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d3f0ab59c2
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Remove -power token until option is fixed
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2019-05-23 19:26:25 -06:00 |
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AurelienUoU
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3811c18953
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Correct syntax error in tokens of regression_fpga_flow.sh
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2019-05-23 18:33:47 -06:00 |
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AurelienUoU
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1018134726
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Update yosys to latest version + add simulation in fpga_flow
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2019-05-23 17:55:49 -06:00 |
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tangxifan
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ee1a24d4ba
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-23 17:38:35 -06:00 |
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tangxifan
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ea8c36ce6e
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upgrade Verilog SB generator using the RRSwitchBlock
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2019-05-23 17:37:39 -06:00 |
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AurelienUoU
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555570c15e
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Update Yosys from version 0.7 to version 0.8
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2019-05-23 16:03:08 -06:00 |
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tangxifan
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ec70bcee99
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-22 22:05:46 -06:00 |
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tangxifan
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4aab93b729
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update class rr_switch_block and be ready for updating the downstream verilog generator
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2019-05-22 22:04:31 -06:00 |
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AurelienUoU
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2b04376209
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Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks
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2019-05-22 13:44:48 -06:00 |
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tangxifan
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502344b13a
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add missing files
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2019-05-22 12:35:12 -06:00 |
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tangxifan
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efbc454cdd
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Add Class for RRSwtichBlock and plug-in to replace the old t_sb
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2019-05-22 12:34:06 -06:00 |
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AurelienUoU
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b4c97f86a3
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Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches
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2019-05-21 17:24:06 -06:00 |
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tangxifan
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d10e05f5cc
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-21 12:16:33 -06:00 |
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tangxifan
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ec3b4c86c4
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update file organization and be ready for SB/CB class
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2019-05-21 12:15:38 -06:00 |
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AurelienUoU
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7192ca212d
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-21 10:36:30 -06:00 |
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AurelienUoU
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199cd99b23
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Add dummy clock name in ace2 commands
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2019-05-21 10:35:12 -06:00 |
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tangxifan
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8186d6dd11
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reorganize files and clean some warnings
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2019-05-21 10:17:54 -06:00 |
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tangxifan
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b185a17359
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add routing_channel unique module generation
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2019-05-20 22:33:17 -06:00 |
giacomin
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ceee28226e
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-20 16:47:07 -06:00 |
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giacomin
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8b520349e7
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fixed a bug for rram based fpga when using explicit verilog port mapping
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2019-05-20 16:44:47 -06:00 |
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AurelienUoU
|
2392d11790
|
Add debug command to understandn travis issue with ace
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2019-05-20 16:06:37 -06:00 |
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AurelienUoU
|
becb90cd16
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Correct syntax error in ace2 log file generation
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2019-05-20 13:56:50 -06:00 |
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AurelienUoU
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fbebb45bf2
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Path correction in config file
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2019-05-20 11:13:30 -06:00 |