tangxifan
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6b703a4fc5
|
add accessors to technology library data structure
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2020-01-17 13:34:32 -07:00 |
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tangxifan
|
622ba9bb8c
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bug fixed in SDC for CBs and SBs: remove useless module names
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2020-01-17 11:24:33 -07:00 |
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tangxifan
|
771f2d9c37
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developing data structure TechnologyLibrary to store technology-related information
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2020-01-17 10:17:15 -07:00 |
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tangxifan
|
aa070b2a41
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further clean-up sample arch.xml
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2020-01-17 09:38:35 -07:00 |
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tangxifan
|
910c69d7e5
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clean up and reorganize XML about technology library
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2020-01-17 09:24:58 -07:00 |
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tangxifan
|
5c69f57559
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sample_arch:move cmos/rram variation to technology library XML nodes
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2020-01-16 20:58:45 -07:00 |
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tangxifan
|
95edd3c091
|
clean up the sample arch
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2020-01-16 20:52:47 -07:00 |
|
tangxifan
|
a598929fe7
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add circuit library checker in the test
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2020-01-16 20:25:00 -07:00 |
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tangxifan
|
f7a7c56366
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move OpenFPGAArch to openfpga namespace
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2020-01-16 20:22:56 -07:00 |
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tangxifan
|
d6adfa0821
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add XML parsing for delay matrix and wire parasitics for circuit library
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2020-01-16 20:14:39 -07:00 |
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tangxifan
|
2e0ce78054
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add XML writing for buffers in circuit library
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2020-01-16 17:21:41 -07:00 |
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tangxifan
|
9ba42cd540
|
add XML writer for circuit ports
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2020-01-16 16:05:11 -07:00 |
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tangxifan
|
0304d723c0
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add XML writer for design technology of a circuit model
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2020-01-16 14:45:41 -07:00 |
|
tangxifan
|
3ace7f8ef7
|
move generic data structures to openfpgautil library
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2020-01-16 13:26:55 -07:00 |
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tangxifan
|
d232391250
|
developed XML writer for circuit library and start porting functions to openfpgautil library
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2020-01-16 12:32:29 -07:00 |
|
tangxifan
|
e282f813bc
|
rename circuit settings to openfpga arch and update sample architecture
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2020-01-15 20:28:04 -07:00 |
|
tangxifan
|
264dc8458d
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add XML parsing for delay matrix in circuit model
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2020-01-15 20:21:53 -07:00 |
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tangxifan
|
602d0bde4c
|
add XML parsing for wire parasitics in circuit model
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2020-01-15 19:54:57 -07:00 |
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tangxifan
|
999c364b25
|
added XML parsing for circuit model ports
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2020-01-15 17:29:49 -07:00 |
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tangxifan
|
c20e1d48d2
|
added XML parsing for pass-gate-logic in circuit models
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2020-01-15 15:49:02 -07:00 |
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tangxifan
|
a9b122d584
|
add XML parsing for buffer models in circuit library
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2020-01-15 15:27:49 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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d0da5ade52
|
Pushing duplicate pin fix for direct list to master branch
Dev
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2020-01-15 09:29:51 -07:00 |
|
tangxifan
|
35d6c9661b
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Finish the first version of XML parser for design technology of circuit models
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2020-01-14 16:24:27 -07:00 |
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tangxifan
|
5937ffc809
|
add XML parsing for buffer/pass-gate-logic -related properties
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2020-01-14 15:44:24 -07:00 |
|
tangxifan
|
9e911cd288
|
bug fixing for direct connection when pin duplication is applied
|
2020-01-14 15:04:47 -07:00 |
|
tangxifan
|
56113e1aab
|
adding XML parsing for design tech of circuit model
|
2020-01-14 14:10:00 -07:00 |
|
tangxifan
|
2692d0fc35
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adding XML parsing for SPICE and Verilog netlist for each circuit model
|
2020-01-14 08:45:27 -07:00 |
|
tangxifan
|
82d83ddceb
|
reorganized the read XML openfpga arch
|
2020-01-14 08:33:48 -07:00 |
|
tangxifan
|
ca3ca14cc7
|
fixed bugs in XML when parsing circuit model types
|
2020-01-13 21:52:13 -07:00 |
|
tangxifan
|
db503ffebf
|
add openfpga read xml executable and start min unit test
|
2020-01-13 21:05:58 -07:00 |
|
tangxifan
|
d6c69ea7c6
|
developing XML parser for circuit model name and type
|
2020-01-12 23:45:51 -07:00 |
|
tangxifan
|
e2f641fdb3
|
add example architecture for openfpga and developing XML parser
|
2020-01-12 22:39:38 -07:00 |
|
tangxifan
|
2e986608ba
|
initial commit on parser for reading openfpga arch xml
|
2020-01-12 21:33:28 -07:00 |
|
tangxifan
|
5dea648be6
|
add missing CMakeList for libarchopenfpga
|
2020-01-12 18:15:36 -07:00 |
|
tangxifan
|
48ecb6e48b
|
immigrate XML parser for circuit_lib to library readarchopenfpga
|
2020-01-12 18:11:00 -07:00 |
ganeshgore
|
15ffdc03f0
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2020-01-09 17:15:04 -07:00 |
|
ganeshgore
|
f0bed1244c
|
Added blif file folding before VPR run
|
2020-01-09 16:50:34 -07:00 |
AurelienAlacchi
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44ba0d826f
|
Merge pull request #39 from LNIS-Projects/dev
Remove redundant net source addition in CBs and SBs
|
2020-01-09 13:37:15 -07:00 |
|
tangxifan
|
747fa09a0c
|
Merge branch 'refactoring' into dev
|
2020-01-08 20:01:40 -07:00 |
|
tangxifan
|
2a3950470e
|
remove redudant net source addition in cbs and sbs
|
2020-01-08 19:43:53 -07:00 |
|
tangxifan
|
8a34de95fd
|
Merge branch 'refactoring' into dev
|
2020-01-08 14:23:26 -07:00 |
|
tangxifan
|
f67981afa8
|
update ducoumentation to explain lib_name XML syntax
|
2020-01-08 14:22:17 -07:00 |
|
tangxifan
|
4c9d380161
|
Merge pull request #38 from LNIS-Projects/dev
architecture fix for tutorial purpose
|
2020-01-07 18:42:21 -07:00 |
AurelienUoU
|
ee7b1c9b1d
|
Update architecture for tutorial
|
2020-01-07 10:08:04 -07:00 |
|
AurelienUoU
|
9e74c3ba5a
|
Merge branch 'master' into dev
|
2020-01-07 10:04:14 -07:00 |
|
AurelienAlacchi
|
701d3964d2
|
Merge pull request #35 from skulis/dockerfile_fix
Fix docker file (do not run make multi threaded)
|
2020-01-07 10:01:08 -07:00 |
BaudouinChauviere
|
9701428413
|
Merge pull request #36 from skulis/fix_tuto
Fix tutorial configuration file
|
2020-01-06 01:21:01 -07:00 |
Szymon Kulis
|
9a6370a7d0
|
Do not run make with -j in Docker
|
2020-01-05 22:02:38 +01:00 |
|
Szymon Kulis
|
895aca1bf1
|
Use template variables
|
2020-01-05 20:39:10 +01:00 |
|
tangxifan
|
4877cfd36a
|
modify the git ignore list for ctags so that we only ignore those tags in specific folders
This is to avoid any source files to be missed when they are placed in a folder called tags.
Libtatum is any example!
|
2020-01-03 21:17:40 -07:00 |