taoli4rs
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cfc0d08060
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Add constrain_pin_location command in openfpga; add full flow test.
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2022-07-20 11:51:00 -07:00 |
tangxifan
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6719a9aa26
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[test] update golden netlists/testbenches etc.
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2022-05-22 13:03:01 +08:00 |
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tangxifan
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22c4d72358
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[test] add a test case to validate negative edge-triggered ff
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2022-05-09 16:57:42 +08:00 |
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tangxifan
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efc25aa66e
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[Script] Fixed a bug in wrong paths
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2022-04-13 16:04:33 +08:00 |
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tangxifan
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5beefda3bd
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[Test] Add a new test case to validate the fix_pins option
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2022-04-13 15:55:21 +08:00 |
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tangxifan
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f8845f7d3a
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[Test] Add a test case to validate separated clock pins in global port
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2022-03-20 11:02:07 +08:00 |
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tangxifan
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fdaf97e60d
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[Test] Update test case by using GPIO with config_done signals
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2022-02-24 09:49:34 -08:00 |
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tangxifan
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a615c9d4e3
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[Test] Rename test cases
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2022-02-24 09:43:41 -08:00 |
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tangxifan
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b27a04eb24
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[Test] Now test case has a config done CCFF
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2022-02-23 22:07:11 -08:00 |
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tangxifan
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245c7b1e45
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[Test] Add a new test case to validate config enable signal in preconfigured testbenches
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2022-02-23 16:02:00 -08:00 |
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tangxifan
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e33ba667e4
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[Test] Add missing file
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2022-02-20 10:59:44 -08:00 |
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tangxifan
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f30de1085c
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[Test] Cover all the related testcase about bus group
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2022-02-19 23:33:16 -08:00 |
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tangxifan
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b4202f52b4
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[Test] debugging
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2022-02-19 23:26:29 -08:00 |
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tangxifan
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785bb1633d
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[Test] trying to see if we support busgroup per benchmark in task configuration file
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2022-02-19 23:23:36 -08:00 |
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tangxifan
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7645d5332d
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[Test] Update bug group examples on the big endian support
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2022-02-18 23:09:03 -08:00 |
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tangxifan
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f0ce1e79a3
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[Test] Added a new test to validate bus group in full testbench
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2022-02-18 15:43:21 -08:00 |
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tangxifan
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223575cf3e
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[Test] Added a new test for bus group on full testbenches
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2022-02-18 15:33:29 -08:00 |
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tangxifan
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5ab84e1861
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[Test] Add a new test for bus group
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2022-02-18 15:29:33 -08:00 |
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tangxifan
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b4d59fdd1e
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[Test] Update bus group file due to little and big endian conversion during yosys/vpr
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2022-02-18 15:02:08 -08:00 |
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tangxifan
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36543f7f2f
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[Script] Support simplified rewriting for Yosys on output verilog
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2022-02-18 14:54:39 -08:00 |
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tangxifan
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8ba3d06392
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[Test] Fixed bugs in simulation settings
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2022-02-18 12:36:22 -08:00 |
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tangxifan
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a4d5172b7c
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[Test] Fixed bugs that causes VPR failed
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2022-02-18 12:31:29 -08:00 |
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tangxifan
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7176037bc4
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[Test] Added a new test about bus group
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2022-02-18 12:26:00 -08:00 |
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tangxifan
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f002c79a61
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[Test] Adapt pin constraints due to changes in pin names
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2022-02-15 16:06:46 -08:00 |
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tangxifan
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b533fd17d5
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[Test] Rework pin constraints that cause problems
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2022-02-15 15:41:16 -08:00 |
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tangxifan
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9ef7ad64d8
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[Test] Simplify paths
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2022-02-15 15:35:21 -08:00 |
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tangxifan
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f8ef3df560
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[Test] Now use 4x4 fabric in testing write_rr_gsb commands
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2022-01-26 11:41:48 -08:00 |
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tangxifan
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3b7588cd48
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[Test] Rename test case to be consistent with the name of options
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2022-01-26 11:25:54 -08:00 |
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tangxifan
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6b26ed0819
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[Test] Add test cases on writing gsb files
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2022-01-26 11:22:39 -08:00 |
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tangxifan
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23795d6474
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[Test] Update golden netlists
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2022-01-25 20:37:08 -08:00 |
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tangxifan
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a9e6b7c12e
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[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
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2022-01-25 20:33:49 -08:00 |
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tangxifan
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fedb1bd2e3
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[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
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2022-01-25 16:41:36 -08:00 |
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tangxifan
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6e778a74ee
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[Test] Add golden reference for files outputted without time stamp
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2022-01-25 16:24:25 -08:00 |
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tangxifan
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2bee59c6ca
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[Test] Add the testcase to validate ``--no_time_stamp``
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2022-01-25 16:21:15 -08:00 |
Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
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Aram Kostanyan
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397f2e71f1
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Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
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2022-01-19 20:43:26 +05:00 |
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Aram Kostanyan
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588ee14920
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Merge branch 'master' into issue-483
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2022-01-18 13:38:12 +05:00 |
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Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
Awais Abbas
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598c5e6b75
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Test case for yosys-only flow added
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2022-01-14 15:37:47 +05:00 |
nadeemyaseen-rs
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1ea56b2d18
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-11-18 00:00:55 +05:00 |
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Aram Kostanyan
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b332a5a1b4
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Added 'basic_tests/verific_test' test-case.
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2021-11-01 18:20:57 +05:00 |
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tangxifan
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b2c4e3314e
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[Test] Bug fix in test cases
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2021-10-11 10:28:09 -07:00 |
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tangxifan
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8566e2a0cd
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[Test] Renaming test case to follow naming convention as other fabric key test cases
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2021-10-11 09:56:23 -07:00 |
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tangxifan
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b8b02d37d5
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[Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file
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2021-10-11 09:53:23 -07:00 |
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tangxifan
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6122863548
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[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
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2021-10-09 20:44:28 -07:00 |
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tangxifan
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a1eaacf5a8
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[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
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2021-10-06 12:12:15 -07:00 |
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tangxifan
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b98a8ec718
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[Test] Added the dedicated test case for fixed shift register clock frequency
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2021-10-06 12:09:26 -07:00 |
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tangxifan
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b21f212031
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[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
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2021-10-05 11:39:53 -07:00 |
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tangxifan
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52569f808e
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[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
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2021-10-05 10:57:33 -07:00 |
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tangxifan
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fa1908511d
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[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
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2021-10-04 16:36:20 -07:00 |