tangxifan
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373566416c
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-16 16:47:21 -07:00 |
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tangxifan
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a8d7b6c2c4
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[script] add a python script for users to visualize the I/O sequence
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2022-09-16 10:49:10 -07:00 |
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tangxifan
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a2e22787c2
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[test] deploy the new test cases to the basic regression tests
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2022-09-16 10:31:15 -07:00 |
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tangxifan
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10e86d334a
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[test] add test cases to validate the various layouts where I/Os are in the center of the grid
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2022-09-16 10:29:19 -07:00 |
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tangxifan
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f2e13e5ea9
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[arch] add more flexible layout to test I/O center features
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2022-09-16 10:00:08 -07:00 |
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tangxifan
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ec38b3990f
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[arch] update to check OpenFPGA I/O indexing
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2022-09-14 13:58:12 -07:00 |
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tangxifan
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83c89ae1bf
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[arch] add more corner case to test the custom I/O location feature
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2022-09-13 23:05:41 -07:00 |
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tangxifan
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330785635d
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[test] now use a bigger fabric for the test case on custom I/O location
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2022-09-13 17:53:33 -07:00 |
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tangxifan
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a37e270f25
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[arch] now custom I/O loc test case cover I/Os in the center of the fabric
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2022-09-13 16:57:18 -07:00 |
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tangxifan
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1c2192a87d
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[engine] fixed a few bugs
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2022-09-12 16:50:32 -07:00 |
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tangxifan
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0d6e4e3979
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[test] add a new example for the repack options
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2022-09-12 16:21:49 -07:00 |
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tangxifan
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a3d070ac6f
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[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst
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2022-09-12 10:43:21 -07:00 |
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tangxifan
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314f5395b4
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[benchmark] fixed a bug which causes yosys failed
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2022-09-09 17:04:59 -07:00 |
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tangxifan
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91fe27ff66
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[test] deploy new test to ci
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2022-09-09 17:00:28 -07:00 |
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tangxifan
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1ab7590603
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[test] added a new test case to
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2022-09-09 16:59:06 -07:00 |
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tangxifan
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cc974a80f7
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[arch] added a new architecture to test the local routing architecture where reset is on LUT
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2022-09-09 16:48:10 -07:00 |
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tangxifan
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7a38c7dd18
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[benchmark] add a new benchmark to test reset signal to drive both lut and ff
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2022-09-09 16:42:55 -07:00 |
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tangxifan
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95d7a17b3c
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Merge branch 'master' into vtr_upgrade
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2022-09-09 14:32:42 -07:00 |
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tangxifan
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d4523e819c
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[test] fixed a bug
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2022-09-08 16:55:50 -07:00 |
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tangxifan
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419a3a1e46
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[arch] fixed a bug
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2022-09-08 16:53:52 -07:00 |
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tangxifan
|
122a323668
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[arch] fixed bugs
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2022-09-08 16:50:33 -07:00 |
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tangxifan
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d76f3e3b6c
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[test] fixed the bug
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2022-09-08 16:34:23 -07:00 |
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tangxifan
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218e6d0a47
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[arch] fixed syntax errors
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2022-09-08 16:31:52 -07:00 |
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tangxifan
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a840aeea7a
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[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
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2022-09-08 16:27:11 -07:00 |
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tangxifan
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b1fad0b4e5
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[arch] add an example architecture to show the use extended syntax
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2022-09-08 16:19:21 -07:00 |
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tangxifan
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56619f9a47
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-07 15:04:05 -07:00 |
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tangxifan
|
477e2119d7
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[test] remove abs paths in golden outputs without time stamps
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2022-09-06 15:24:43 -07:00 |
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tangxifan
|
93ab992187
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[test] update golden outputs without time stamps
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2022-09-06 14:59:00 -07:00 |
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tangxifan
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561d0a6545
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[test] add more test case to track golden outputs for representative fpga sizes
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2022-09-06 14:04:23 -07:00 |
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tangxifan
|
9e1abf5898
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Merge branch 'master' into vtr_upgrade
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2022-09-01 21:39:14 -07:00 |
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tangxifan
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c48f750f86
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[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
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2022-09-01 20:10:29 -07:00 |
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tangxifan
|
c691eb0e95
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Merge branch 'master' into vtr_upgrade
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2022-09-01 15:54:14 -07:00 |
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tangxifan
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51dc082bd4
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[test] force a fixed routing chan W for no time stamp test case
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2022-09-01 15:02:40 -07:00 |
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tangxifan
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d86eb04c5d
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[test] now no timestamp test case covers gsb files
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2022-09-01 14:03:51 -07:00 |
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tangxifan
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71ad0721a1
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Merge branch 'master' into vtr_upgrade
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2022-08-31 13:56:17 -07:00 |
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tangxifan
|
201bca8968
|
[test] typo
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2022-08-30 08:59:20 -07:00 |
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tangxifan
|
5f88b9a226
|
[test] typo
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2022-08-29 22:41:15 -07:00 |
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tangxifan
|
0b5bdcdbb1
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[test] deploy new test to basic regression tests
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2022-08-29 22:07:56 -07:00 |
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tangxifan
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069e2b00b1
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[test] add more test cases to validate gsb options
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2022-08-29 22:03:06 -07:00 |
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tangxifan
|
dbacee8a0a
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[script] turn off equivalent for soft adder architecture as we do not expect any routing optimization
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2022-08-27 20:25:50 -07:00 |
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tangxifan
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ef3381a1b2
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[script] also turn off pb_pin_fixup in vpr for quicklogic tests
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2022-08-27 20:07:49 -07:00 |
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tangxifan
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b9fade4c76
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[script] turn off the pb_pin_fix_up in vpr run for mcnc and vtr benchmarks
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2022-08-27 20:04:29 -07:00 |
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tangxifan
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e9d6e7e38a
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[engine] update vtr and enable more debugging info
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2022-08-27 19:12:43 -07:00 |
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tangxifan
|
8d6682c28b
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[test] fixed a bug when removing previous runs
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2022-08-25 16:20:18 -07:00 |
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tangxifan
|
fa790d50d4
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[script] fixed a bug on wrong path to the ace2 executable
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2022-08-23 10:53:44 -07:00 |
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tangxifan
|
bdb051f787
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[arch] update arch files
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2022-08-22 18:24:37 -07:00 |
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tangxifan
|
6c44f321e5
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[script] fixed a bug
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2022-08-22 18:24:26 -07:00 |
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tangxifan
|
2bbf2f02c9
|
[script] now return status on each arch upgrade task
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2022-08-22 18:23:00 -07:00 |
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tangxifan
|
b6e1175517
|
[script] update doc and avoid modify README.MD when updating arch files
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2022-08-22 18:19:23 -07:00 |
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tangxifan
|
8d45903dc2
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[script] makefile for vpr arch
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2022-08-22 18:13:48 -07:00 |