tangxifan
|
c54f3905d5
|
fixed broken fpga flow
|
2019-06-28 13:07:04 -06:00 |
|
tangxifan
|
0902d1e75a
|
c++ string is not working, use char which is stable
|
2019-06-13 18:38:46 -06:00 |
|
tangxifan
|
0f1ed19ad0
|
Revert to the use of sprintf instead std::string. Have no idea why string is not working
|
2019-06-07 18:54:57 -06:00 |
AurelienUoU
|
a2f6ded2a2
|
Add path modification in file changing a keyword into OpenFPGA full path
|
2019-06-04 15:21:15 -06:00 |
|
AurelienUoU
|
ba05a08ef0
|
Path correction in tech debugging + correction of yosys rewrite file in fpga_flow
|
2019-05-30 09:52:19 -06:00 |
|
AurelienUoU
|
2b04376209
|
Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks
|
2019-05-22 13:44:48 -06:00 |
|
AurelienUoU
|
b4c97f86a3
|
Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches
|
2019-05-21 17:24:06 -06:00 |
|
AurelienUoU
|
df8bb0db1a
|
Add MCNC Benchmarks netlists generation to travis regression test
|
2019-05-17 15:22:04 -06:00 |
Baudouin Chauviere
|
79f3db9880
|
removed the now useless tutorial part
|
2018-12-10 13:57:01 -07:00 |
|
Baudouin Chauviere
|
d55ecd154b
|
Add the PTM to the benchmark flow
|
2018-11-21 11:32:34 -07:00 |
|
Baudouin Chauviere
|
15d69e2bb1
|
Generation script finished TODO: integration in flow
|
2018-11-20 13:24:31 -07:00 |
Baudouin Chauviere
|
9611576d6a
|
Update on the examples to respect the new syntax
|
2018-11-19 15:50:29 -07:00 |
|
Baudouin Chauviere
|
dddca8acbb
|
Global Makefile and typo correction
|
2018-10-24 17:34:51 -06:00 |
Xifan Tang
|
158dec405e
|
Reorganize the code directory
|
2018-07-26 11:28:21 -06:00 |