tangxifan
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f284f6f8d0
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[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
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2020-09-20 12:03:10 -06:00 |
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tangxifan
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8b6c8f73e9
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[OpenFPGA code] fix bug for clang compatibility
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2020-09-14 21:26:53 -06:00 |
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tangxifan
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c31d36deb6
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[Regression Tests] Deploy output buffer only routing multiplexer testcase to CI
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2020-09-14 16:16:03 -06:00 |
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tangxifan
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9c66a35bf6
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[arch language] Now circuit library will automatically identify the default circuit model if needed
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2020-08-23 14:06:03 -06:00 |
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tangxifan
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b83319bf14
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[Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group
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2020-08-23 13:48:22 -06:00 |
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tangxifan
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161d660837
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update documentation for the initial offset when mapping physical pins
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2020-08-19 15:00:46 -06:00 |
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tangxifan
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3eea12ceae
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added a new XML syntax: initial offset for physical mode pin mapping
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2020-08-19 14:43:44 -06:00 |
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tangxifan
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2712c354a9
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now physical pb_port binding support multiple ports
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2020-08-18 12:38:56 -06:00 |
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tangxifan
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a3d22c56e3
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bug fix in FPGA-SPICE
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2020-07-24 19:51:32 -06:00 |
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tangxifan
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6d046efc52
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add max_width to technology library XML syntax to support multi-bin transistor in FPGA-SPICE
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2020-07-24 16:25:27 -06:00 |
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tangxifan
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f573fa3ee0
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move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
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2020-07-22 18:47:12 -06:00 |
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tangxifan
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de4586217f
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now device binding is not mandatory for circuit models
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2020-07-14 12:04:22 -06:00 |
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tangxifan
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e2b492f184
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add circuit model tech binding
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2020-07-13 20:35:10 -06:00 |
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tangxifan
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f081cef495
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add fabric key library
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2020-06-12 00:07:04 -06:00 |
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tangxifan
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58807bfcb3
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remove simulation settings from openfpga arch data structure
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2020-06-11 19:31:16 -06:00 |
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tangxifan
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f26550141f
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add missing files
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2020-06-11 19:31:16 -06:00 |
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tangxifan
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15f087598c
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split simulation settings to a separated XML file
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2020-06-11 19:31:15 -06:00 |
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tangxifan
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8267dad8ef
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add decoder support for Z signals
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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65df309419
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bug fixing for frame-based configuration protocol and rename some naming function to be generic
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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3a0d3b4e95
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fix the broken CI/regression tests due to incorrect file path
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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3a26bb5eef
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add advanced check in configurable memories
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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62c506182c
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start developing frame-based configuration protocol
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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f52b5d5b4c
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use error code in read_arch command
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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8ac6e10727
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bug fix in lut and mux module generation on supporting spypads
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2020-04-22 14:41:16 -06:00 |
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tangxifan
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e6c896d583
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now inout must be global port and I/O port so that it will appear in the top-level module
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2020-04-08 16:54:08 -06:00 |
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tangxifan
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6eb125ec2a
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Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML
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2020-04-06 14:09:52 -06:00 |
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tangxifan
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5f4e7dc5d4
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support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
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tangxifan
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8b583b7917
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debugging spy port builder in module manager
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2020-04-05 16:01:25 -06:00 |
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tangxifan
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ff9cc50527
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relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
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2020-03-27 20:09:50 -06:00 |
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tangxifan
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b035b4c87f
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debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
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2020-02-21 12:16:50 -07:00 |
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tangxifan
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59c13550e0
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add direct annotation with inter-column/row syntax
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2020-02-14 17:40:59 -07:00 |
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tangxifan
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df3ae60954
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add default configurable memory model set-up when reading openfpga architecture XML
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2020-02-12 15:19:40 -07:00 |
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tangxifan
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87f1ca1151
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add naming fix-up report generation
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2020-01-29 18:56:47 -07:00 |
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tangxifan
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24b180b298
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change the mode bit storage in annotation data structure from string to vector of integers
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2020-01-29 11:59:20 -07:00 |
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tangxifan
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7d4b07421d
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finish XML parser and writer for pb_type annotation
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2020-01-26 15:54:49 -07:00 |
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tangxifan
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1cba141dd0
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add pb parser and support XML parsing for pb type name in full hiearchy
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2020-01-26 11:52:58 -07:00 |
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tangxifan
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cd3565cf53
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complete the XML parser for pb_type annotation
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2020-01-26 10:56:57 -07:00 |
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tangxifan
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a9f03ce21b
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add XML attribute parsing for physical and operating pb_type annotation
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2020-01-26 10:19:47 -07:00 |
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tangxifan
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bafd866cfc
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start developing XML parser for pb_type annotation
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2020-01-25 21:19:08 -07:00 |
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tangxifan
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b6f96e5a8f
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add method functions to pb_type annotation
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2020-01-25 20:46:21 -07:00 |
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tangxifan
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9b4b6ae083
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rename pb_annotation and move it to openfpga namespace
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2020-01-25 18:17:00 -07:00 |
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tangxifan
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f834954698
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start developing the pb_type annotation
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2020-01-25 18:14:38 -07:00 |
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tangxifan
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b4f4bf62a2
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add comments to sample arch
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2020-01-25 17:42:24 -07:00 |
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tangxifan
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7feeee8c0e
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add full syntax to sample_arch.xml about the physical pb_type binding
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2020-01-25 17:38:06 -07:00 |
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tangxifan
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655f84b00e
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add write_openfpga_arch command to openfpga shell
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2020-01-23 20:58:15 -07:00 |
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tangxifan
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a03f8aa346
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add profiling for read arch
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2020-01-23 20:12:30 -07:00 |
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tangxifan
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cdb3b6de46
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add read_openfpga_arch to OpenFPGA shell
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2020-01-23 19:10:53 -07:00 |
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tangxifan
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16752b7e39
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update on sample arch
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2020-01-20 12:42:08 -07:00 |
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tangxifan
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07994d424c
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add XML parser and writer for direct connection
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2020-01-19 15:00:19 -07:00 |
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tangxifan
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10336cbe67
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add XML parser and writer for routing circuit definition for OpenFPGA architecture
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2020-01-19 14:44:27 -07:00 |