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3172 Commits

Author SHA1 Message Date
tangxifan ccd9ebe71b [Documentation] Use travis.com in CI badge as travis.org will be deprecated by the end of 2020 2020-09-17 16:59:20 -06:00
tangxifan 681e80d4b6 [Regression tests] update frac_lut test case using more representative benchmarks 2020-09-17 10:39:22 -06:00
tangxifan 367cf59efd [Benchmark] Bug fix in the and2_or2 benchmark 2020-09-17 10:35:13 -06:00
tangxifan de48b8c7b2 [Benchmark] Add a new micro benchmark to test fracturable LUTs 2020-09-17 10:21:25 -06:00
Laboratory for Nano Integrated Systems (LNIS) 92690f6b1e
Merge pull request #85 from LNIS-Projects/dev 
Support on flexible local routing architecture
 2020-09-16 19:59:54 -06:00
tangxifan 9cfb2f52ef [OpenFPGA code] bug fix for fully equivalent outputs of pb_type 2020-09-16 19:26:46 -06:00
tangxifan ca1bafc688 [OpenFPGA Architecture] Add full pin equivalence to full output crossbar architecture 2020-09-16 19:26:12 -06:00
tangxifan 2aff461f59 [Regression Tests] Deploy no local routing test case to CI 2020-09-16 18:09:24 -06:00
tangxifan c22d8e2421 [Architecture] Bug fix in no local routing architecture 2020-09-16 18:07:52 -06:00
tangxifan c40c9f5876 [Regression test] add test case for no local routing architecture 2020-09-16 18:05:33 -06:00
tangxifan f5b7ac6269 [OpenFPGA Architecture] Add a new architecture with no local routing 2020-09-16 18:04:55 -06:00
tangxifan 5fe039dd7c [Regression Tests] Deploy the fully connected crossbar test to CI 2020-09-16 17:35:49 -06:00
tangxifan 35d47ee0e7 [Regression tests] bug fix in the test case for fully connected output crossbar 2020-09-16 17:33:54 -06:00
tangxifan 030d7f02f8 [OpenFPGA architecture] bug fix in the fully connected output crossbar architecture 2020-09-16 17:30:08 -06:00
tangxifan 30fb99095f [Regression Tests] Add new test case for fully connected output crossbar 2020-09-16 17:29:15 -06:00
tangxifan 3c0faf0021 [OpenFPGA Architecture] Add a new architecture with fully connected crossbar at CLB outputs 2020-09-16 17:27:24 -06:00
Laboratory for Nano Integrated Systems (LNIS) bcbc583593
Merge pull request #84 from LNIS-Projects/dev 
Add compiler compatibility tests to Travis CI
 2020-09-14 23:18:55 -06:00
tangxifan 8b6c8f73e9 [OpenFPGA code] fix bug for clang compatibility 2020-09-14 21:26:53 -06:00
tangxifan b43cd2741d [Regression Tests] Add gcc-5 compatibility test to Travis CI 2020-09-14 20:14:16 -06:00
tangxifan c23742c751 [OpenFPGA code] fix bug for clang compatibility 2020-09-14 20:13:27 -06:00
tangxifan fc6bfdc7a2 [OpenFPGA Code] Patch syntax compatibility for older gcc 2020-09-14 18:55:21 -06:00
tangxifan d4bac95cd4 [Regression Tests] Enable matrix eval parameter in setting up compilers 2020-09-14 17:07:14 -06:00
tangxifan c08d4f5cd9 [Regression Test] Patch travis script 2020-09-14 16:59:08 -06:00
tangxifan e3559f0df9 [Regression Test] Add compiler coverage test to CI 2020-09-14 16:53:16 -06:00
tangxifan e155360656
Merge pull request #83 from LNIS-Projects/dev 
Enriched regression test for flexible routing multiplexer designs
 2020-09-14 16:43:54 -06:00
tangxifan c31d36deb6 [Regression Tests] Deploy output buffer only routing multiplexer testcase to CI 2020-09-14 16:16:03 -06:00
tangxifan f149c88548 [Regression Test] Deploy input buffer only multiplexer testcase to CI 2020-09-14 16:11:48 -06:00
tangxifan f42411c29e [Regression Tests] Add test cases for routing multiplexer design with input/output buffers only 2020-09-14 16:03:43 -06:00
tangxifan aaf63050bb [OpenFPGA architecture] Add the architecture where routing multiplexers have only output buffers 2020-09-14 15:58:34 -06:00
tangxifan aa9521b23b [OpenFPGA architecture] Add the architecture where routing multiplexers have only input buffers 2020-09-14 15:57:44 -06:00
tangxifan a03f2fe974 [Regression Test] Deploy the debuf mux test case to CI 2020-09-14 15:48:08 -06:00
tangxifan eecfd186f0 [OpenFPGA Architecture] Add the openfpga architecture for multiplexers without buffers 2020-09-14 15:46:10 -06:00
tangxifan 9bf0e772a3 [Regression Tests]Add a new testcase for routing multiplexer designs without buffers 2020-09-14 15:45:35 -06:00
Laboratory for Nano Integrated Systems (LNIS) 486a187460
Merge pull request #81 from LNIS-Projects/dev 
Update documentation and debugging aid
 2020-09-02 23:32:57 -06:00
tangxifan 7a2502ddf9 [documentation] add more guidelines about the vpr-openfpga architecture annotation 2020-09-02 22:47:14 -06:00
tangxifan 04070fd4ca [Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker 2020-09-02 22:16:10 -06:00
tangxifan b5251ce5af [documentation] update motivation figure and layout licenses 2020-09-01 11:07:50 -06:00
Laboratory for Nano Integrated Systems (LNIS) 70b8bd1a76
Merge pull request #79 from LNIS-Projects/dev 
[Architecture Languange] Patch the default circuit model definition
 2020-08-23 16:20:24 -06:00
tangxifan 4b3142c4ee [Architecture File] Patch openfpga architecture with default circuit model definition 2020-08-23 15:13:28 -06:00
tangxifan 9101ba1021 [Architecture Language] Update openfpga architecture files for default models 2020-08-23 14:55:44 -06:00
tangxifan ac8e937a50 [Documentation] Update for default circuit model rules 2020-08-23 14:08:38 -06:00
tangxifan 9c66a35bf6 [arch language] Now circuit library will automatically identify the default circuit model if needed 2020-08-23 14:06:03 -06:00
tangxifan b83319bf14 [Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group 2020-08-23 13:48:22 -06:00
Laboratory for Nano Integrated Systems (LNIS) 551c2d79c2
Merge pull request #77 from LNIS-Projects/dev 
Misc Updates
 2020-08-20 09:18:23 -06:00
tangxifan fb5a5a2448 [documentation] remove the limitation on through channels 2020-08-19 20:12:49 -06:00
tangxifan 6c925dcded [regression test] Add more tests for thru channels and deploy to CI 2020-08-19 20:11:37 -06:00
tangxifan 1a3e020174 deploy through channel test case to CI 2020-08-19 20:04:01 -06:00
tangxifan 8041c90f12 bug fix in through channel support in tileable routing 2020-08-19 20:01:50 -06:00
tangxifan 881672d46a update thru channel arch for avoid buggy pin locations 2020-08-19 19:52:35 -06:00
tangxifan 47f15729ad update doc about the limitation on using tileable routing 2020-08-19 18:37:28 -06:00