Commit Graph

35 Commits

Author SHA1 Message Date
tangxifan cc0114459a [Doc] Enrich examples for LUT circuit models 2020-11-26 13:03:12 -07:00
tangxifan 62e804215b [Doc] Add svg figures for LUT examples 2020-11-26 12:35:39 -07:00
tangxifan 2b9a97729e [Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models 2020-11-23 15:09:47 -07:00
tangxifan f6126d1ed6 [Doc] Add illustrative example to diff between global ports definitions 2020-11-12 09:24:39 -07:00
tangxifan bc43c876b0 [Doc] Update documentation for the rules in global port definition for tile ports 2020-11-11 14:10:11 -07:00
tangxifan 2c269c532a [Doc] Update doc for the global port definition using physical tile port 2020-11-10 20:48:28 -07:00
tangxifan 056b7c0c79 [Doc] Update documentation about CCFF circuit model examples 2020-11-06 12:22:22 -07:00
tangxifan 849ecc7fc0 [Doc] Add notes for using the is_data_io syntax 2020-11-05 09:30:19 -07:00
tangxifan 9bce2f3818 [Doc] Update documentation for new XML syntax "is_data_io" 2020-11-05 09:28:46 -07:00
tangxifan 7e940980e1 [Doc] Update documentation about configuration regions for frame-based protocol 2020-10-30 21:52:01 -06:00
tangxifan c2c384e24b [Doc] update documentation about memory bank definition 2020-10-29 17:04:25 -06:00
tangxifan ccaa697e5a [Documentation] Add links to technical features to examples 2020-10-10 22:40:37 -06:00
tangxifan 639d57016b [Documentation] Update documentation about the multi-region configuration 2020-09-29 15:55:42 -06:00
tangxifan 462886fb5f [Documentation] Update documentation for the multiple region support on configuration chain 2020-09-29 14:02:03 -06:00
tangxifan 7a2502ddf9 [documentation] add more guidelines about the vpr-openfpga architecture annotation 2020-09-02 22:47:14 -06:00
tangxifan ac8e937a50 [Documentation] Update for default circuit model rules 2020-08-23 14:08:38 -06:00
tangxifan fb5a5a2448 [documentation] remove the limitation on through channels 2020-08-19 20:12:49 -06:00
tangxifan 47f15729ad update doc about the limitation on using tileable routing 2020-08-19 18:37:28 -06:00
tangxifan d6d17675e2 update docoumentation about the constraints when using tileable rr_graph generator 2020-08-19 18:01:32 -06:00
tangxifan 161d660837 update documentation for the initial offset when mapping physical pins 2020-08-19 15:00:46 -06:00
tangxifan 53f87f44b4 update documentation for the multi-port support in physical pb_pin 2020-08-18 12:44:38 -06:00
tangxifan c3fd817bae update documentation about new XML syntax max width 2020-07-24 16:33:01 -06:00
tangxifan 862d71f57a remove obselete vpr7 XML syntax from documentation 2020-07-15 11:13:47 -06:00
tangxifan cb0df2c1c6 update doc about technology binding between circuit library and device library 2020-07-15 11:05:33 -06:00
tangxifan 65dfc545c1 update documentation for fabric key 2020-07-07 10:28:29 -06:00
tangxifan 7615db2be6 update documentation for the new fabric key rules 2020-07-06 16:44:21 -06:00
tangxifan 933801cfa7 update documentation about alias support in fabric key 2020-06-27 15:04:04 -06:00
tangxifan ba38120093 add documentation for fabric key and reorganize command references 2020-06-12 16:15:16 -06:00
tangxifan 1a006f2ddb update documentation for separated XML files 2020-06-11 19:31:16 -06:00
tangxifan b9dd47d465 update documentation about memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan c00653961e minor format fix in documentation 2020-06-11 19:31:13 -06:00
tangxifan fe2ba7d50a update documentation for standalone configuration protocol 2020-06-11 19:31:13 -06:00
tangxifan de07712a3a update documentation about the frame-based configuration protocol 2020-06-11 19:31:11 -06:00
tangxifan f079c61bd3 re organize tutorials 2020-06-11 19:31:08 -06:00
tangxifan c27d77a418 clean-up documentation for a shallow hierarchy 2020-06-11 19:31:08 -06:00