Commit Graph

87 Commits

Author SHA1 Message Date
ganeshgore ea4122a8a4 Updated openfpga_flow and task file to support sheel run 2020-04-06 00:34:36 -06:00
ganeshgore d1d3446568 backedup partial upgrade for fpga_flow script 2020-04-05 11:36:24 -06:00
ganeshgore 46bb5ef9d0 Added disp option in openfpga_flow, Default is --nodisp 2020-01-23 10:04:38 -07:00
ganeshgore f0bed1244c Added blif file folding before VPR run 2020-01-09 16:50:34 -07:00
ganeshgore 74b650e9e1 Added fpga_x2p_duplicate_grid_pin option 2019-12-30 12:25:28 -07:00
ganeshgore d1e260f54f Spice related option added 2019-12-30 12:16:04 -07:00
Ganesh Gore 6bb11918dc Updated modelsim and collected result 2019-11-16 19:10:04 -07:00
Ganesh Gore 333d10c94c Added vpr_fpga_verilog_print_simulation_ini option 2019-11-15 14:26:57 -07:00
Ganesh Gore a880802803 Bug Fix: Corrected read VPR stat filename 2019-11-01 20:51:05 -06:00
Ganesh Gore 595d2d3070 Simple argument shuffle 2019-11-01 18:21:26 -06:00
Ganesh Gore 81180939ca Bug fix: Missing exit_if_fail flag in fpga_flow script 2019-10-31 09:56:57 -06:00
Ganesh Gore c034b871bb Made activity file independent of power option 2019-10-15 16:08:25 -06:00
Ganesh Gore eaf8ecee86 added _vpr.txt subscript to vpr log files 2019-10-15 16:07:34 -06:00
Ganesh Gore cd5fd6ce6c Added explicit checking to VVP execution 2019-09-18 12:14:26 -06:00
Ganesh Gore 169732ccc1 Added verbose option in VVP output 2019-09-17 22:09:37 -06:00
Ganesh Gore 678e3181ba Made compact_routing_hierarchy options uncond 2019-09-16 21:22:13 -06:00
Ganesh Gore 81b9c5b266 Added flag for VVP exit code 2019-09-14 12:35:47 -06:00
Ganesh Gore 702a7683a8 Ensure strict exit of fpga_flow on error 2019-09-05 10:23:35 -06:00
Ganesh Gore f4e99c150a resolve missing variable bug 2019-08-31 21:55:32 -06:00
Ganesh Gore 06c0dbb328 Added docuementation for fpga_flow 2019-08-31 15:19:34 -06:00
Ganesh Gore 02137805c7 Added python version check in flow and task scripts 2019-08-29 22:14:30 -06:00
Ganesh Gore f558437ae1 Added task for vpr_blif flow 2019-08-25 00:23:39 -06:00
Ganesh Gore 6e7de16ad4 Solved bug in commnad rearrangement 2019-08-22 23:41:25 -06:00
Ganesh Gore 77e2a7bca3 Added execution time logs in flow script 2019-08-22 17:01:38 -06:00
Ganesh Gore 30cbe38d3d Added Test Modes - Added blif VPR Option 2019-08-22 17:00:59 -06:00
Ganesh Gore a335a57c6c Added debug option to commnad line arguments 2019-08-21 11:08:13 -06:00
Ganesh Gore b7484ef178 Removed traces of old template file 2019-08-20 15:58:19 -06:00
Ganesh Gore 08b0ef3550 Updated validate_command_line_arguments function
+ Checks if valid flow is provided as a argument
+ Command line argument list validated with dependencies provided in configuration file
2019-08-19 21:28:23 -06:00
Ganesh Gore 53941eaf5c Changed yosys output file name 2019-08-19 19:06:46 -06:00
Ganesh Gore 8f8707ff98 Added option to filter results after parsing 2019-08-19 19:04:14 -06:00
Ganesh Gore 7f6c1b3e00 Code re-arrangement
+ Added support for subdirectory task in openfpga_task
+ Rearranged function order
+ Combined vpr re-route and standrad run function
+ Removed external_call function from fpga_flow script
+ Added .gitignore to task directory
2019-08-18 12:26:05 -06:00
Ganesh Gore 12c998c12a Added dockerignore + minor changes in openfpga_flow script 2019-08-17 16:22:52 -06:00
Ganesh Gore c43c3cdf25 Added VPR output parse option 2019-08-16 13:36:39 -06:00
Ganesh Gore effbd332aa Added task report generation 2019-08-16 10:59:44 -06:00
Ganesh Gore 901932a4fc First draft: Working openfpga task flow 2019-08-16 09:44:50 -06:00
Ganesh Gore 5d3708651e Added fpga_flow and fpga_task script
+ Missed local intermediate commits
2019-08-15 14:39:58 -06:00
Ganesh Gore 9ab57d1b2e Added fpga_flow script - Working Yosys 2019-08-09 16:49:05 -06:00