tangxifan
|
0c329866da
|
[engine] Use RRGraphView in openfpga source codes
|
2022-08-16 16:48:32 -07:00 |
|
tangxifan
|
4d67864c2c
|
[Engine] Now global port can be connected partial pins of a tile port
|
2022-03-20 11:36:03 +08:00 |
|
tangxifan
|
cbbf601edc
|
[Tool] Fix a compiler warning due to uninitialized data structure
|
2021-06-18 16:20:13 -06:00 |
|
tangxifan
|
c8d41b4e69
|
[Tool] Change routing module port naming to include architecture port names
|
2021-03-14 19:35:49 -06:00 |
|
tangxifan
|
956b9aca01
|
[Tool] Trim dead codes in port naming function
|
2021-03-13 20:23:08 -07:00 |
|
tangxifan
|
2c5634ee76
|
[Tool] Change pin naming of grid modules to be related to architecture port names
|
2021-03-13 20:05:18 -07:00 |
|
tangxifan
|
c0da6b900a
|
[Tool] Bug fix in creating multi-bit clock port connections
|
2021-01-12 18:38:00 -07:00 |
|
tangxifan
|
65b2fe3ab7
|
[Tool] Bug fix in the global tile connection by considering all the subtiles
|
2021-01-10 11:52:38 -07:00 |
|
tangxifan
|
9a441fa5cc
|
[Tool] Upgrade openfpga to support extended global tile port definition
|
2021-01-09 18:47:12 -07:00 |
|
tangxifan
|
372fb261fd
|
[Tool] Extend the support on global tile port for I/O tiles
|
2020-11-11 15:09:40 -07:00 |
|
tangxifan
|
9cbc374b33
|
[Tool] Add check codes for tile annotation
|
2020-11-11 12:03:13 -07:00 |
|
tangxifan
|
c61ec5a8b8
|
[Tool] Bug fix for defining global ports from tiles
|
2020-11-10 20:31:14 -07:00 |
|
tangxifan
|
cbb1545ee3
|
[Tool] Add connection builder for tile global ports to top-level module
|
2020-11-10 16:59:00 -07:00 |
|
tangxifan
|
81ecfa3197
|
add comments to clarify how to select CB ports when connecting to SBs at the top level
|
2020-07-01 14:44:40 -06:00 |
|
tangxifan
|
0a3c746fb1
|
now split CB module bus ports into lower/upper parts
|
2020-07-01 14:37:13 -06:00 |
|
tangxifan
|
2e7684b746
|
adapt bus ports in connection block module builder
|
2020-06-30 17:50:53 -06:00 |
|
tangxifan
|
2ef083c49d
|
adapt SB module builder to use bus ports
|
2020-06-30 16:02:40 -06:00 |
|
tangxifan
|
025d4a3599
|
use efficient net builder in top module connection builder
|
2020-06-29 23:28:26 -06:00 |
|
tangxifan
|
e7d5736269
|
add profile time to top module builder for better spot on runtime/memory overhead sources
|
2020-06-29 23:17:03 -06:00 |
|
tangxifan
|
4bf0a63ae6
|
bug fixed for multiple io types defined in FPGA architectures
|
2020-03-27 16:32:15 -06:00 |
|
tangxifan
|
b6bdf78d95
|
bug fixed for heterogeneous block instances in top module
|
2020-03-24 17:39:26 -06:00 |
|
tangxifan
|
fc6abc13fd
|
add physical tile utils to identify pins that have Fc=0
|
2020-03-21 21:02:47 -06:00 |
|
tangxifan
|
9dc9c2c9f7
|
add build top module connection functions
|
2020-02-14 10:45:24 -07:00 |