tangxifan
|
8378ad4bf3
|
[engine] fixed a bug on mistakenly adding I/O child modules for direct connections
|
2022-09-14 17:13:23 -07:00 |
github-actions[bot]
|
2b2fc6020d
|
Updated Patch Count
|
2022-09-15 00:02:45 +00:00 |
|
tangxifan
|
036933dc14
|
[engine] fixed more bugs due to the extra modules added to top-level module when using memory bank or frame-based protocols
|
2022-09-14 16:46:10 -07:00 |
|
tangxifan
|
0425b00af5
|
[engine] fixed a bug for frame-based protocols
|
2022-09-14 16:41:30 -07:00 |
|
tangxifan
|
cb89488f76
|
[engine] now support a custom list for indexing I/O children in each module
|
2022-09-14 15:54:55 -07:00 |
|
tangxifan
|
ec38b3990f
|
[arch] update to check OpenFPGA I/O indexing
|
2022-09-14 13:58:12 -07:00 |
|
tangxifan
|
0781f1ca3b
|
Merge branch 'io_center' of github.com:lnis-uofu/OpenFPGA into io_center
|
2022-09-14 11:31:03 -07:00 |
|
tangxifan
|
eb8b7e6901
|
[engine] fixed a bug in i/o indexing
|
2022-09-14 11:30:34 -07:00 |
|
tangxifan
|
83c89ae1bf
|
[arch] add more corner case to test the custom I/O location feature
|
2022-09-13 23:05:41 -07:00 |
|
tangxifan
|
330785635d
|
[test] now use a bigger fabric for the test case on custom I/O location
|
2022-09-13 17:53:33 -07:00 |
|
tangxifan
|
a37e270f25
|
[arch] now custom I/O loc test case cover I/Os in the center of the fabric
|
2022-09-13 16:57:18 -07:00 |
|
tangxifan
|
18cf3615ea
|
Merge pull request #780 from lnis-uofu/rst_lut_in
Test reset signal from a global network to drive an LUT input
|
2022-09-12 18:22:03 -07:00 |
|
tangxifan
|
48f776d49b
|
[doc] update documentation about the new option
|
2022-09-12 16:58:32 -07:00 |
|
tangxifan
|
1c2192a87d
|
[engine] fixed a few bugs
|
2022-09-12 16:50:32 -07:00 |
|
tangxifan
|
0d6e4e3979
|
[test] add a new example for the repack options
|
2022-09-12 16:21:49 -07:00 |
|
tangxifan
|
2fc124e109
|
[engine] now repack has a new option "--ignore_global_nets_on_pins"
|
2022-09-12 16:18:26 -07:00 |
|
tangxifan
|
a3d070ac6f
|
[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst
|
2022-09-12 10:43:21 -07:00 |
|
tangxifan
|
314f5395b4
|
[benchmark] fixed a bug which causes yosys failed
|
2022-09-09 17:04:59 -07:00 |
|
tangxifan
|
91fe27ff66
|
[test] deploy new test to ci
|
2022-09-09 17:00:28 -07:00 |
|
tangxifan
|
1ab7590603
|
[test] added a new test case to
|
2022-09-09 16:59:06 -07:00 |
|
tangxifan
|
cc974a80f7
|
[arch] added a new architecture to test the local routing architecture where reset is on LUT
|
2022-09-09 16:48:10 -07:00 |
|
tangxifan
|
7a38c7dd18
|
[benchmark] add a new benchmark to test reset signal to drive both lut and ff
|
2022-09-09 16:42:55 -07:00 |
|
tangxifan
|
266da6dd4c
|
[engine] update vtr
|
2022-09-09 15:02:46 -07:00 |
|
tangxifan
|
8bd55babb0
|
[engine] update vtr
|
2022-09-09 15:00:22 -07:00 |
|
tangxifan
|
95d7a17b3c
|
Merge branch 'master' into vtr_upgrade
|
2022-09-09 14:32:42 -07:00 |
|
tangxifan
|
390c0526b5
|
Merge pull request #777 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2022-09-09 12:20:48 -07:00 |
|
github-actions[bot]
|
9632934ab1
|
Updated Patch Count
|
2022-09-09 19:19:21 +00:00 |
|
tangxifan
|
f2a311aecf
|
Merge pull request #775 from lnis-uofu/subtile_syntax
Subtile syntax
|
2022-09-08 18:43:15 -07:00 |
|
tangxifan
|
0609210b39
|
[doc] update doc with the new xml syntax
|
2022-09-08 17:00:16 -07:00 |
|
tangxifan
|
d4523e819c
|
[test] fixed a bug
|
2022-09-08 16:55:50 -07:00 |
|
tangxifan
|
419a3a1e46
|
[arch] fixed a bug
|
2022-09-08 16:53:52 -07:00 |
|
tangxifan
|
7fe240e199
|
[vpr] fixed a bug when parsing conventional pin loc
|
2022-09-08 16:53:00 -07:00 |
|
tangxifan
|
122a323668
|
[arch] fixed bugs
|
2022-09-08 16:50:33 -07:00 |
|
tangxifan
|
765712a263
|
[vpr] fixed a bug when parsing instances
|
2022-09-08 16:47:28 -07:00 |
|
tangxifan
|
d76f3e3b6c
|
[test] fixed the bug
|
2022-09-08 16:34:23 -07:00 |
|
tangxifan
|
218e6d0a47
|
[arch] fixed syntax errors
|
2022-09-08 16:31:52 -07:00 |
|
tangxifan
|
a840aeea7a
|
[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
|
2022-09-08 16:27:11 -07:00 |
|
tangxifan
|
b1fad0b4e5
|
[arch] add an example architecture to show the use extended syntax
|
2022-09-08 16:19:21 -07:00 |
|
tangxifan
|
c71b533e9f
|
[vpr] syntax
|
2022-09-08 16:04:25 -07:00 |
|
tangxifan
|
b943d79092
|
[vpr] now support the definition of subtile in custom pin location, such io[3:4].a2f[0:0]
|
2022-09-08 15:57:08 -07:00 |
|
tangxifan
|
cd112ce703
|
Merge branch 'master' into vtr_upgrade
|
2022-09-08 09:25:37 -07:00 |
|
tangxifan
|
1073c3306b
|
Merge pull request #770 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2022-09-07 17:05:00 -07:00 |
|
github-actions[bot]
|
89d5119c01
|
Updated Patch Count
|
2022-09-08 00:03:40 +00:00 |
|
tangxifan
|
f74f1a6603
|
[engine] update vtr
|
2022-09-07 16:24:03 -07:00 |
|
tangxifan
|
148bf5e830
|
[engine] update vtr
|
2022-09-07 16:20:13 -07:00 |
|
tangxifan
|
e5c7a3df9f
|
[engine] syntax
|
2022-09-07 15:51:54 -07:00 |
|
tangxifan
|
a81de4efed
|
[engine] update vtr
|
2022-09-07 15:10:17 -07:00 |
|
tangxifan
|
56619f9a47
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-07 15:04:05 -07:00 |
Ganesh Gore
|
65d7f592c9
|
Merge pull request #766 from lnis-uofu/rr_gsb_mirror
Now switch_id is no longer a metric to fail GSB mirrorable functions but circuit model is.
|
2022-09-06 22:58:37 -06:00 |
|
tangxifan
|
3e4bc985fe
|
Merge branch 'rr_gsb_mirror' of github.com:lnis-uofu/OpenFPGA into rr_gsb_mirror
|
2022-09-07 11:57:15 +08:00 |