tangxifan
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7424b59de1
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Merge pull request #786 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-09-14 17:32:22 -07:00 |
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tangxifan
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8378ad4bf3
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[engine] fixed a bug on mistakenly adding I/O child modules for direct connections
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2022-09-14 17:13:23 -07:00 |
github-actions[bot]
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2b2fc6020d
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Updated Patch Count
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2022-09-15 00:02:45 +00:00 |
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tangxifan
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036933dc14
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[engine] fixed more bugs due to the extra modules added to top-level module when using memory bank or frame-based protocols
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2022-09-14 16:46:10 -07:00 |
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tangxifan
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0425b00af5
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[engine] fixed a bug for frame-based protocols
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2022-09-14 16:41:30 -07:00 |
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tangxifan
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cb89488f76
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[engine] now support a custom list for indexing I/O children in each module
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2022-09-14 15:54:55 -07:00 |
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tangxifan
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ec38b3990f
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[arch] update to check OpenFPGA I/O indexing
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2022-09-14 13:58:12 -07:00 |
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tangxifan
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0781f1ca3b
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Merge branch 'io_center' of github.com:lnis-uofu/OpenFPGA into io_center
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2022-09-14 11:31:03 -07:00 |
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tangxifan
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eb8b7e6901
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[engine] fixed a bug in i/o indexing
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2022-09-14 11:30:34 -07:00 |
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tangxifan
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83c89ae1bf
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[arch] add more corner case to test the custom I/O location feature
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2022-09-13 23:05:41 -07:00 |
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tangxifan
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330785635d
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[test] now use a bigger fabric for the test case on custom I/O location
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2022-09-13 17:53:33 -07:00 |
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tangxifan
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a37e270f25
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[arch] now custom I/O loc test case cover I/Os in the center of the fabric
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2022-09-13 16:57:18 -07:00 |
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tangxifan
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18cf3615ea
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Merge pull request #780 from lnis-uofu/rst_lut_in
Test reset signal from a global network to drive an LUT input
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2022-09-12 18:22:03 -07:00 |
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tangxifan
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48f776d49b
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[doc] update documentation about the new option
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2022-09-12 16:58:32 -07:00 |
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tangxifan
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1c2192a87d
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[engine] fixed a few bugs
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2022-09-12 16:50:32 -07:00 |
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tangxifan
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0d6e4e3979
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[test] add a new example for the repack options
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2022-09-12 16:21:49 -07:00 |
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tangxifan
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2fc124e109
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[engine] now repack has a new option "--ignore_global_nets_on_pins"
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2022-09-12 16:18:26 -07:00 |
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tangxifan
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a3d070ac6f
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[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst
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2022-09-12 10:43:21 -07:00 |
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tangxifan
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314f5395b4
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[benchmark] fixed a bug which causes yosys failed
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2022-09-09 17:04:59 -07:00 |
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tangxifan
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91fe27ff66
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[test] deploy new test to ci
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2022-09-09 17:00:28 -07:00 |
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tangxifan
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1ab7590603
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[test] added a new test case to
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2022-09-09 16:59:06 -07:00 |
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tangxifan
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cc974a80f7
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[arch] added a new architecture to test the local routing architecture where reset is on LUT
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2022-09-09 16:48:10 -07:00 |
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tangxifan
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7a38c7dd18
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[benchmark] add a new benchmark to test reset signal to drive both lut and ff
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2022-09-09 16:42:55 -07:00 |
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tangxifan
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266da6dd4c
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[engine] update vtr
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2022-09-09 15:02:46 -07:00 |
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tangxifan
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8bd55babb0
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[engine] update vtr
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2022-09-09 15:00:22 -07:00 |
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tangxifan
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95d7a17b3c
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Merge branch 'master' into vtr_upgrade
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2022-09-09 14:32:42 -07:00 |
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tangxifan
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390c0526b5
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Merge pull request #777 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-09-09 12:20:48 -07:00 |
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github-actions[bot]
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9632934ab1
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Updated Patch Count
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2022-09-09 19:19:21 +00:00 |
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tangxifan
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f2a311aecf
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Merge pull request #775 from lnis-uofu/subtile_syntax
Subtile syntax
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2022-09-08 18:43:15 -07:00 |
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tangxifan
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0609210b39
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[doc] update doc with the new xml syntax
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2022-09-08 17:00:16 -07:00 |
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tangxifan
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d4523e819c
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[test] fixed a bug
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2022-09-08 16:55:50 -07:00 |
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tangxifan
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419a3a1e46
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[arch] fixed a bug
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2022-09-08 16:53:52 -07:00 |
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tangxifan
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7fe240e199
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[vpr] fixed a bug when parsing conventional pin loc
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2022-09-08 16:53:00 -07:00 |
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tangxifan
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122a323668
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[arch] fixed bugs
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2022-09-08 16:50:33 -07:00 |
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tangxifan
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765712a263
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[vpr] fixed a bug when parsing instances
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2022-09-08 16:47:28 -07:00 |
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tangxifan
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d76f3e3b6c
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[test] fixed the bug
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2022-09-08 16:34:23 -07:00 |
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tangxifan
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218e6d0a47
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[arch] fixed syntax errors
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2022-09-08 16:31:52 -07:00 |
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tangxifan
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a840aeea7a
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[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
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2022-09-08 16:27:11 -07:00 |
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tangxifan
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b1fad0b4e5
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[arch] add an example architecture to show the use extended syntax
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2022-09-08 16:19:21 -07:00 |
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tangxifan
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c71b533e9f
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[vpr] syntax
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2022-09-08 16:04:25 -07:00 |
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tangxifan
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b943d79092
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[vpr] now support the definition of subtile in custom pin location, such io[3:4].a2f[0:0]
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2022-09-08 15:57:08 -07:00 |
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tangxifan
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cd112ce703
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Merge branch 'master' into vtr_upgrade
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2022-09-08 09:25:37 -07:00 |
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tangxifan
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1073c3306b
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Merge pull request #770 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-09-07 17:05:00 -07:00 |
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github-actions[bot]
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89d5119c01
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Updated Patch Count
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2022-09-08 00:03:40 +00:00 |
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tangxifan
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f74f1a6603
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[engine] update vtr
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2022-09-07 16:24:03 -07:00 |
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tangxifan
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148bf5e830
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[engine] update vtr
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2022-09-07 16:20:13 -07:00 |
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tangxifan
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e5c7a3df9f
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[engine] syntax
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2022-09-07 15:51:54 -07:00 |
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tangxifan
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a81de4efed
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[engine] update vtr
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2022-09-07 15:10:17 -07:00 |
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tangxifan
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56619f9a47
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-07 15:04:05 -07:00 |
Ganesh Gore
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65d7f592c9
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Merge pull request #766 from lnis-uofu/rr_gsb_mirror
Now switch_id is no longer a metric to fail GSB mirrorable functions but circuit model is.
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2022-09-06 22:58:37 -06:00 |