Baudouin Chauviere
|
69014704ef
|
Explicit verilog final push
|
2019-07-16 13:13:30 -06:00 |
Ganesh Gore
|
443a73954f
|
Removed all local files
+ Removed local configurations and scripts from previous commit
|
2019-07-03 14:26:06 -06:00 |
Ganesh Gore
|
1093e341a8
|
Added additional architecure files
|
2019-06-11 11:26:44 -06:00 |
AurelienUoU
|
74ee6bad7f
|
Update spice path in architecture
|
2019-05-29 10:08:58 -06:00 |
AurelienUoU
|
ffdcd4bb9c
|
Path correction 2
|
2019-05-28 11:59:09 -06:00 |
AurelienUoU
|
20f80a73e7
|
Correct path to tech files
|
2019-05-28 11:24:03 -06:00 |
tangxifan
|
4b852afeac
|
skip rotating mirror detection which is too time-consuming
|
2019-05-25 23:41:46 -06:00 |
tangxifan
|
d3eae80e64
|
implemented an native way in finding rotable Switch blocks
|
2019-05-25 19:37:18 -06:00 |
AurelienUoU
|
4f921b03da
|
Add travis full path to avoid missing sources
|
2019-05-16 15:51:10 -06:00 |
AurelienUoU
|
57d75520a6
|
Verilog verification with Travis
|
2019-05-15 15:57:05 -06:00 |
AurelienUoU
|
a3656dde45
|
Add missing Verilog source, Archictecture folder and Testbenches correction
|
2019-05-13 16:41:35 -06:00 |
tangxifan
|
46d44fa42a
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
tangxifan
|
5e36aa82c5
|
fixa bug in determining mux structure
|
2019-01-22 13:54:50 -07:00 |
Baudouin Chauviere
|
510c27f816
|
Removed commercial scripts, replaced by academia ones
|
2019-01-09 11:56:07 -07:00 |
Baudouin Chauviere
|
3b4fc16c60
|
Adding help message on the go.sh
|
2019-01-09 11:54:28 -07:00 |
tangxifan
|
66701838ff
|
update relative path in ARCH XML
|
2019-01-08 11:41:24 -07:00 |
tangxifan
|
ee6b1d6cd6
|
adapt arch xml and act for demo
|
2018-12-13 22:46:40 -07:00 |
AurelienUoU
|
5e94b7093d
|
Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)
|
2018-12-08 22:57:54 -07:00 |