Commit Graph

485 Commits

Author SHA1 Message Date
tangxifan c16bcd7f63 [doc] add file formates required by pcf2place 2022-07-28 16:35:13 -07:00
tangxifan 860591ff3f [doc] add pcf file format to documentation 2022-07-28 16:15:44 -07:00
tangxifan 6e5fde56ce [doc] add pcf2place to command list 2022-07-28 16:06:57 -07:00
tangxifan 2b4beb632c [doc] fix a bug in including io information file format 2022-07-26 15:50:35 -07:00
tangxifan bf2b1da801 [doc] add the new command file format to documentation 2022-07-26 14:06:07 -07:00
tangxifan 21a0415ff3
Update compile.rst 2022-07-21 17:52:21 -07:00
tangxifan 929c74b3b0 Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into hotfix_reg 2022-05-23 09:11:18 +08:00
tangxifan 7a0f796b7c [doc] add missing file link and show version number in frontpage README 2022-05-22 15:27:22 +08:00
tangxifan 78313b3593 [Misc] Now version number is in a separated file; Cmakefile and doc read the file and build version number on fly; CI can also update version 2022-05-22 15:22:43 +08:00
tangxifan 1794578b49 [doc] code format 2022-05-22 14:04:12 +08:00
tangxifan 07df4611e8 [doc] more tips 2022-05-22 13:46:13 +08:00
tangxifan 61a1462c21 [doc] add guidelines about running regression tests 2022-05-22 13:44:48 +08:00
Ganesh Gore daae02a614 Minor documentation update 2022-05-08 13:03:16 -06:00
Ganesh Gore 1e243650b9 Added option to copy example projects 2022-05-03 14:06:16 -06:00
Ganesh Gore 42567d8178 Updated docuementation 2022-05-02 12:56:31 -06:00
tangxifan 907308ee0f [Doc] Update bitstream distribution file format 2022-03-29 20:09:24 +08:00
taoli4rs 781250f0bb Fix a small typo to trigger the CI flow. 2022-03-22 16:36:45 -07:00
tangxifan 6ff69d26b9 [Doc] An example to the documentation about the new feature in tile_annotation 2022-03-20 13:12:13 +08:00
tangxifan 123bb70cb3 [Doc] More explanantion on the use of config_enable attribute for circuit ports 2022-02-23 15:53:58 -08:00
tangxifan b78e58d9bf [Doc] Update doc about big endian syntax in bus group file format 2022-02-18 23:07:18 -08:00
tangxifan 8116141210 [Doc] Update documentation on the bus group feature 2022-02-18 15:46:25 -08:00
tangxifan 37d8617a5c [Doc] Update due to new options 2022-02-17 19:45:37 -08:00
tangxifan 4a78bcf5d3 [Doc] update file format about bus group 2022-02-17 15:15:05 -08:00
tangxifan f5e0d685cf [Doc] Adjust figure width 2022-02-17 14:29:09 -08:00
tangxifan 796428d848 [Doc] Add documentation about bus group file format 2022-02-17 14:22:21 -08:00
tangxifan 2b5fded2a9 [Doc] Update documentation on the new option 2022-02-01 13:25:58 -08:00
tangxifan b7b0a2a5d8 [Doc] Update doc about the new option 2022-02-01 12:19:26 -08:00
tangxifan 63f44adf15 [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
tangxifan a9a56686e2 [Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml`` 2022-01-26 11:10:29 -08:00
tangxifan 25143d07f1 [FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files 2022-01-25 13:37:54 -08:00
tangxifan a4659020f2
Merge branch 'master' into time_stamp 2022-01-25 12:11:35 -08:00
tangxifan 62b57b05d2 [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
Aram Kostanyan 758453f725 Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections. 2022-01-21 02:21:00 +05:00
Aram Kostanyan bd158311c5 Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark. 2022-01-18 14:07:41 +05:00
Aram Kostanyan 588ee14920 Merge branch 'master' into issue-483 2022-01-18 13:38:12 +05:00
Aram Kostanyan fb2e4377c8 Added missing changes from previous commit. 2022-01-17 19:42:40 +05:00
Aram Kostanyan 2b008177e7 Updated documentation. 2022-01-17 14:58:20 +05:00
Awais Abbas 54d4f30592 OpenFPGA Documentation updated for yosys only support 2022-01-14 16:14:48 +05:00
tangxifan 80c6d5887d Merge branch 'ql_mem_bank_opensource' of https://github.com/RapidSilicon/OpenFPGA_RS into ql_mem_bank 2021-12-29 10:57:46 -08:00
tangxifan b2ba0d0c42 [Doc] Add version naming convention to developer guidelines 2021-12-22 15:12:14 -08:00
nadeemyaseen-rs 236910cde4 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-12-09 00:00:21 +05:00
tangxifan 1e5afb985c
Update contact.rst 2021-11-30 20:25:15 -08:00
nadeemyaseen-rs 1ea56b2d18 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-11-18 00:00:55 +05:00
Aram Kostanyan a355977420 Adding Yosys+Verific support. 2021-10-29 18:34:27 +05:00
tangxifan b8d5920529 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream 2021-10-28 15:45:58 -07:00
Ganesh Gore 130805d50c Updated CI documentation 2021-10-21 15:17:30 -06:00
nadeemyaseen-rs e0cfd46ec7 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-10-14 19:25:31 +05:00
tangxifan 57159fc121 [Doc] Update documentation for the new syntax in configuration protocol and fabric key file format 2021-10-10 17:46:45 -07:00
tangxifan 40b589dc6d [Doc] Update documentation about the clock definition for programming clocks in simulation settings 2021-10-06 13:50:33 -07:00
tangxifan 03bcf6dee5 [Doc] Update documenation for the new option ``--keep_dont_care_bits`` 2021-10-05 19:23:42 -07:00