bbleaptrot
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8431337f39
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Fix grammar errors in fig captions and elsewhere
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2021-04-19 09:36:13 -06:00 |
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bbleaptrot
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86c856d35a
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Fix reference links
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2021-04-19 09:25:54 -06:00 |
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bbleaptrot
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cd6beb5789
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Add one more link to fabric_netlists
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2021-04-19 09:14:47 -06:00 |
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bbleaptrot
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f8810940c3
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Update links
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2021-04-19 09:10:17 -06:00 |
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bbleaptrot
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fcb7ee3283
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Update to properly reference fabric netlist page
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2021-04-19 09:05:30 -06:00 |
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bbleaptrot
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5010fb1e7f
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Update hyperlinks
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2021-04-19 08:52:05 -06:00 |
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bbleaptrot
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291638ee0f
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Trying to resolve hyperlink to right location
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2021-04-19 08:45:02 -06:00 |
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bbleaptrot
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beed1ce31e
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replace hyperlink with more stable :ref: link
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2021-04-19 08:38:09 -06:00 |
tangxifan
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e85402eaaa
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Merge pull request #293 from lnis-uofu/dff_techmap
Enable correct reset stimuli in testbench generators
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2021-04-18 17:15:28 -06:00 |
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tangxifan
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0b49c22682
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[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
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2021-04-18 16:11:11 -06:00 |
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tangxifan
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82dd09a180
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Merge branch 'master' into dff_techmap
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2021-04-18 12:09:52 -06:00 |
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tangxifan
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6550ea3dfa
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[Tool] Rework pin constarint API to avoid expose raw data to judge for developers
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2021-04-18 12:02:49 -06:00 |
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tangxifan
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0e65442afd
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Merge pull request #292 from lnis-uofu/dff_techmap
Verilog testbench generator now accepts pin constraints on non-clock global ports
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2021-04-17 23:02:35 -06:00 |
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tangxifan
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6e9b24f9bf
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[Tool] Patch the invalid pin constraint net name
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2021-04-17 19:56:30 -06:00 |
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tangxifan
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253422e7b7
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[Tool] Bugfix due to refactoring
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2021-04-17 19:27:03 -06:00 |
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tangxifan
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02ca51d84b
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[Tool] Reorganize functions in full testbench generator to avoid big-chunk codes
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2021-04-17 17:45:50 -06:00 |
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tangxifan
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d95a1e2776
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[Tool] Encapulate search function in PinConstraint data structure
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2021-04-17 17:31:55 -06:00 |
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tangxifan
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da619fabe7
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[Tool] FPGA-Verilog testbench generator accepts pin constraints in full testbench
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2021-04-17 17:19:34 -06:00 |
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tangxifan
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03a709dce9
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Merge branch 'master' into dff_techmap
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2021-04-17 16:20:55 -06:00 |
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tangxifan
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6e1b58f8a6
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[Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports
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2021-04-17 15:05:22 -06:00 |
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tangxifan
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7018073e28
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[Script] Update openfpga shell script w/o ace usage to adapt pin constraint files
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2021-04-17 15:04:51 -06:00 |
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tangxifan
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da95da933b
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[Test] Add pin constraint file to map reset to correct FPGA pins
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2021-04-17 15:04:26 -06:00 |
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tangxifan
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64b2700979
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Merge branch 'master' into tutorials
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2021-04-17 10:19:30 -06:00 |
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tangxifan
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8c5eb5e1d7
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Merge pull request #291 from lnis-uofu/dff_techmap
Support DFF with asynchronous reset in tech mapping
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2021-04-16 21:52:22 -06:00 |
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tangxifan
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e3dafe99da
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[Arch] Revert to old version arch due to editing by mistake
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2021-04-16 20:58:32 -06:00 |
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tangxifan
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c020333512
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Merge branch 'master' into dff_techmap
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2021-04-16 20:54:28 -06:00 |
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tangxifan
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7172fc9ea1
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[Test] Patch test for architecture using asynchronous DFFs
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2021-04-16 20:48:37 -06:00 |
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tangxifan
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0a15f366cb
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[HDL] Patch dff models used in yosys tech map
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2021-04-16 20:48:15 -06:00 |
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tangxifan
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16e02ef485
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[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
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2021-04-16 20:47:39 -06:00 |
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tangxifan
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1c2f91b7e6
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[Script] Patch yosys script with dff tech map
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2021-04-16 20:47:18 -06:00 |
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tangxifan
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2666726f36
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[Script] Remove clock routing from example openfpga shell script without ace
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2021-04-16 20:46:49 -06:00 |
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tangxifan
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23d08757cf
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[Script] Add example script without using ACE2
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2021-04-16 20:20:10 -06:00 |
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tangxifan
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bbdc0e53af
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[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures
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2021-04-16 20:14:48 -06:00 |
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tangxifan
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b11d03f9c5
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[Test] Deploy new test to CI
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2021-04-16 20:01:40 -06:00 |
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tangxifan
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93be81abe1
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[Test] Add test case for architecture using DFF with reset
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2021-04-16 20:00:48 -06:00 |
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tangxifan
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5414a6a3da
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[Script] Add yosys script with custom DFF tech mapping
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2021-04-16 20:00:30 -06:00 |
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tangxifan
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4239bb4e68
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[Arch] Patch architecture files using multi-mode DFFs
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2021-04-16 19:59:55 -06:00 |
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tangxifan
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f2f7f010ea
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[Arch] Add new architectures using DFF with reset in VPR
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2021-04-16 19:26:18 -06:00 |
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tangxifan
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64294ae4eb
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[Doc] Update README for architecture files due to new architecture features
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2021-04-16 19:25:54 -06:00 |
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tangxifan
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71df9700ea
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Merge pull request #290 from lnis-uofu/iwls2005
[WIP] Add opencore RTLs from IWLS 2005 benchmarks
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2021-04-16 17:41:05 -06:00 |
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tangxifan
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ff4460695b
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[HDL] Add dff tech map files for yosys
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2021-04-16 17:00:55 -06:00 |
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tangxifan
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e46c6e75a3
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[Benchmark] Add missing RTL for IWLS2005 benchmarks
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2021-04-16 16:50:41 -06:00 |
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tangxifan
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f395ed2718
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[Test] Deploy iwls tests to CI
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2021-04-16 16:13:46 -06:00 |
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tangxifan
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87587bbb74
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[Test] Add iwls2005 benchmarks to regression tests
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2021-04-16 16:12:05 -06:00 |
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tangxifan
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1566a5558a
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[Test] Add task configuration file for iwls2005
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2021-04-16 16:10:31 -06:00 |
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tangxifan
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43bf016576
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[Script] Add example openfpga shell script for iwls benchmark
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2021-04-16 16:09:47 -06:00 |
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tangxifan
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26d3b5a954
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[Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches
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2021-04-16 16:08:58 -06:00 |
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tangxifan
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86ad572530
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[Benchmark] Add opencore RTLs from IWLS 2005 benchmarks
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2021-04-16 14:27:54 -06:00 |
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bbleaptrot
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410c6a12ff
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Update figures to be more accurate and clean
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2021-04-16 11:46:12 -06:00 |
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bbleaptrot
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221822f0f0
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update figures to correctly display out ports
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2021-04-16 11:33:01 -06:00 |