Jingrong Lin
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be3546f7e3
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Merge branch 'master' into bin_format
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2024-10-08 13:28:53 +08:00 |
tangxifan
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b9a0b1cdf8
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[core] code format
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2024-10-07 14:21:19 -07:00 |
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tangxifan
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4f96680e1f
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[core] adapt to side var changes
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2024-10-07 14:20:48 -07:00 |
Lin
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bceb160ab8
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reformat code
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2024-09-29 13:20:49 +08:00 |
|
Lin
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7d9a677534
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changed file name
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2024-09-29 13:17:13 +08:00 |
|
Lin
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bddf693d7b
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read bin ready
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2024-09-29 12:22:02 +08:00 |
|
Lin
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08ec3760e4
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mod read bin
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2024-09-29 10:46:50 +08:00 |
|
Lin
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ed381692a7
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read bin format mod (with bug)
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2024-09-27 18:41:30 +08:00 |
|
Lin
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59f1e4adc9
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add read bin (with bugs)
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2024-09-27 18:28:53 +08:00 |
|
Lin
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1d6f9901bb
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renamed file
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2024-09-27 17:23:17 +08:00 |
|
Lin
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ef18d04a3a
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write bin function works now
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2024-09-27 17:21:24 +08:00 |
|
Lin
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3fcdc10d3a
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write bin function no compile error
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2024-09-27 11:34:57 +08:00 |
|
Lin
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0cca4952bc
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write bin format function (with bug)
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2024-09-26 18:01:13 +08:00 |
|
Lin
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5174b7a336
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add capnp for unique blocks and add write bin function
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2024-09-26 17:39:52 +08:00 |
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tangxifan
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c52610959c
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[core] code format
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2024-09-21 21:54:37 -07:00 |
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tangxifan
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f009180bbf
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[core] refactor
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2024-09-21 21:53:53 -07:00 |
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tangxifan
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415fd9a8fa
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[core] code format
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2024-09-21 21:39:30 -07:00 |
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tangxifan
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9e461284d0
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[core] standardize API for clock network intermeidate drivers
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2024-09-21 21:38:32 -07:00 |
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tangxifan
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4e85a6f414
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[core] code format
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2024-09-20 22:37:05 -07:00 |
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tangxifan
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33a253da3d
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[core] fixed the bug
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2024-09-20 22:20:41 -07:00 |
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tangxifan
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6551ca81e5
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[core] debugging
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2024-09-20 19:48:02 -07:00 |
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tangxifan
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2bb87ea278
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[core] code format
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2024-09-20 19:23:14 -07:00 |
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tangxifan
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f87e095558
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[core] support intermediate driver in clock routing
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2024-09-20 19:22:39 -07:00 |
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tangxifan
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e8957b6fd8
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[core] enable clock intermediate driver in rrgraph buildup
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2024-09-20 19:07:16 -07:00 |
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tangxifan
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f6b645fd25
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[core] code format
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2024-09-18 17:44:55 -07:00 |
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tangxifan
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1673d9b919
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[core] fixed a bug
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2024-09-18 17:43:41 -07:00 |
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tangxifan
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82878063c1
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[core] syntax
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2024-09-18 17:32:04 -07:00 |
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tangxifan
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47e30c3e4b
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[core] support last stage mux
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2024-09-18 17:26:44 -07:00 |
|
Lin
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41d38193d3
|
reformat code
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2024-09-12 11:18:25 +08:00 |
|
Lin
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5ccad723c4
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add comments
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2024-09-12 11:16:31 +08:00 |
|
Lin
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55611dbfe7
|
rewrite write_xml function
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2024-09-11 18:08:51 +08:00 |
|
Lin
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b2a5bd8437
|
fix merge error
|
2024-09-11 14:35:24 +08:00 |
|
Jingrong Lin
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77b188060b
|
Merge branch 'master' into preloading_clean
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2024-09-11 11:08:49 +08:00 |
|
Lin
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ae6a8cb604
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fix bug
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2024-09-10 14:34:42 +08:00 |
victorzh001
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04a60ca4b5
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Merge branch 'master' into victor_OpenFPGA_dbg
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2024-09-10 11:01:47 +08:00 |
Victor
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3ea830e168
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Add the reference_file to the index.rst
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2024-09-10 10:46:15 +08:00 |
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tangxifan
|
7250a7d703
|
[core] code format
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2024-09-09 12:46:46 -07:00 |
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tangxifan
|
e3b99e88ff
|
[core] syntax
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2024-09-09 12:46:23 -07:00 |
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tangxifan
|
fc92ecea24
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[core] typo
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2024-09-09 12:43:38 -07:00 |
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tangxifan
|
5f50e4623c
|
[core] add a new option map_global_net_to_msb for pb_pin_fixup
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2024-09-09 12:21:09 -07:00 |
|
Lin
|
f1547bae8a
|
fix build error
|
2024-09-09 18:18:07 +08:00 |
|
tangxifan
|
37cac3d679
|
Merge branch 'master' into victor_OpenFPGA_dbg
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2024-09-08 21:13:48 -07:00 |
|
Lin
|
41d0eb7736
|
modification on device_rr_gsb
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2024-09-09 11:36:48 +08:00 |
|
Lin
|
af7201d4bb
|
fix is_compressed_ tag
|
2024-09-09 11:19:12 +08:00 |
rafljiarui
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f7aaead513
|
Fixed typo in vpr-main.cpp
|
2024-09-06 13:14:59 -05:00 |
|
Victor
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9a2fc86dcd
|
add dependency on build_fabric
|
2024-09-06 17:58:47 +08:00 |
|
Victor
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7bacc781d0
|
update code according to code review comments
|
2024-09-06 15:39:08 +08:00 |
|
Victor
|
4aca4fda6f
|
fix issue in reg test
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2024-09-05 10:43:53 +08:00 |
|
Victor
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ba5c8a3364
|
update code format
|
2024-09-03 11:20:51 +08:00 |
|
Victor
|
0093d4b269
|
Add command report_reference
|
2024-09-02 15:21:50 +08:00 |