tangxifan
|
24a174c7a4
|
[engine] fixed syntax errors
|
2022-11-23 17:06:27 -08:00 |
|
tangxifan
|
07424b1e7f
|
[engine] now main() is encapuslated in a class OpenfpgaShell
|
2022-11-23 16:52:22 -08:00 |
|
tangxifan
|
2d42826919
|
[lib] code format
|
2022-10-21 13:03:03 -07:00 |
|
tangxifan
|
0999c9444b
|
[lib] remove debugging messages
|
2022-10-21 12:44:56 -07:00 |
|
tangxifan
|
b720b49eb1
|
[lib] now count pcf errors
|
2022-10-21 11:48:09 -07:00 |
|
tangxifan
|
c9631497e2
|
[engine] syntax
|
2022-10-17 16:11:49 -07:00 |
|
tangxifan
|
60c448c98d
|
[engine] syntax
|
2022-10-17 15:49:34 -07:00 |
|
tangxifan
|
76862efa57
|
[engine] syntax
|
2022-10-17 15:46:19 -07:00 |
|
tangxifan
|
c3f180372d
|
[engine] do not error out when ql-style is used in pin table
|
2022-10-17 15:42:22 -07:00 |
|
tangxifan
|
0f2b8da7f0
|
[engine] code format
|
2022-10-17 14:55:34 -07:00 |
|
tangxifan
|
63d8b00630
|
[engine] syntax
|
2022-10-17 14:54:18 -07:00 |
|
tangxifan
|
811438c20e
|
[engine] syntax
|
2022-10-17 14:20:23 -07:00 |
|
tangxifan
|
11624cd0c6
|
[engine] enabling new feature: pin_table_direction_convention
|
2022-10-17 14:08:21 -07:00 |
|
tangxifan
|
2f434fd4d3
|
[lib] developing pin dir convention support
|
2022-10-17 12:35:06 -07:00 |
|
tangxifan
|
dbbabbc098
|
[lib] developing the support on forcing pin direction from a specific column in pin table .csv
|
2022-10-17 12:23:39 -07:00 |
|
tangxifan
|
e2debd2dde
|
[engine] add missing header files after coding formatter sorts the include files
|
2022-10-06 18:08:57 -07:00 |
|
tangxifan
|
6d31b319a2
|
[engine] update source files subject to code formatting rules
|
2022-10-06 17:08:50 -07:00 |
|
tangxifan
|
cc6bf85433
|
[cmake] now rename version to short 'OPENFPGA_ENABLE_VERSION'
|
2022-10-03 11:37:41 -07:00 |
|
tangxifan
|
a144794ce6
|
[cmake] skip custom build on version build with an option
|
2022-10-03 11:18:43 -07:00 |
|
tangxifan
|
81e524cec4
|
[CMake] Added a new option 'OPENFPGA_WITH_VERSION_UP_TO_DATE' which allows users to skip version build (by default it remains always on)
|
2022-10-03 11:11:21 -07:00 |
|
tangxifan
|
25f6c529e0
|
[engine] fixed syntax errors when using clang
|
2022-08-25 09:58:43 -07:00 |
|
tangxifan
|
a50392f380
|
[script] update CMakefile to streamline test source files
|
2022-08-24 19:56:35 -07:00 |
|
tangxifan
|
83600d2bdd
|
[script] add install target for lib CMakefile
|
2022-08-24 19:47:01 -07:00 |
|
tangxifan
|
5d6a90d983
|
[engine] remove compile warnings
|
2022-08-22 20:59:50 -07:00 |
|
tangxifan
|
d5f56aada3
|
[lib] typo
|
2022-08-22 18:29:20 -07:00 |
|
tangxifan
|
903dd6cef6
|
[engine] remove warnings
|
2022-08-18 15:56:18 -07:00 |
|
tangxifan
|
2d05462219
|
[lib] remove warnings
|
2022-08-18 15:53:51 -07:00 |
|
tangxifan
|
2957b3aa7f
|
[lib] remove useless header files
|
2022-08-18 15:40:29 -07:00 |
|
tangxifan
|
a52597361b
|
[script] remove duplicated libraries in dependency list for some libopenfpga
|
2022-08-18 11:34:01 -07:00 |
|
tangxifan
|
e909f4fabe
|
[lib] rename libopenfpga to libs
|
2022-08-18 10:27:20 -07:00 |
|
tangxifan
|
075900a7c9
|
[engine] remove out-of-date codes due to the upgrades in VTR submodule
|
2022-08-16 13:56:08 -07:00 |
coolbreeze413
|
9fd8c02e13
|
header inclusions required for MinGW windows build
|
2022-06-29 07:03:38 +05:30 |
Manadher Kharroubi
|
73d9b40124
|
adding Tcl interface to vpr
|
2022-06-07 09:15:20 -07:00 |
Szymon Kulis
|
c4e033ac9b
|
Include limits in argparse.cpp
|
2021-11-28 07:57:31 +01:00 |
|
tangxifan
|
1d96974b99
|
[Tool] Patch to remove compiler warnings
|
2021-02-04 16:54:04 -07:00 |
|
tangxifan
|
2483154c34
|
[Tool] Patch disable_packing XML syntax to be consistent with VPR upstream
|
2021-02-04 16:28:32 -07:00 |
|
tangxifan
|
dd4f83a374
|
bug fixing to constant string to display interconnect names
|
2020-04-07 18:28:19 -06:00 |
|
tangxifan
|
13cd48c119
|
add support on packable/unpackable modes in VPR architecture
|
2020-04-06 16:07:49 -06:00 |
|
tangxifan
|
610c71671f
|
experimentally developing through channels inside multi-width and multi-height grids.
Still debugging.
|
2020-03-24 16:47:45 -06:00 |
|
tangxifan
|
708fda9606
|
fixed a bug in using tileable routing when directlist is enabled
|
2020-03-20 16:38:58 -06:00 |
|
tangxifan
|
a0b150f12e
|
adding micro architecture using adder chain
|
2020-03-20 14:18:59 -06:00 |
|
tangxifan
|
5be118d695
|
tileable rr_graph builder ready to debug
|
2020-03-06 16:18:45 -07:00 |
|
tangxifan
|
2d86a02358
|
refactored LUT bitstream generation to use vtr logic
|
2020-02-25 12:45:13 -07:00 |
|
tangxifan
|
5006a4395d
|
bring RRGraph object and writer online
|
2020-01-31 16:39:40 -07:00 |
|
tangxifan
|
9269d7106d
|
move rr_graph back to vpr because the reader and writer requires too much dependency on the core engine
|
2020-01-31 15:42:44 -07:00 |
|
tangxifan
|
fb0bcd7a48
|
create rr_graph library to enforce unit test on the new data structures as well as compare to legacy rr_node
|
2020-01-31 12:29:50 -07:00 |
|
tangxifan
|
75c3507acf
|
add verbose output option for openfpga linking architecture
|
2020-01-31 11:36:58 -07:00 |
|
tangxifan
|
8a7a4dc48e
|
add physical type annotation for interconnects and inference
|
2020-01-28 21:59:10 -07:00 |
|
tangxifan
|
5ecb771673
|
debugging the annotation to physical mode of pb_types
|
2020-01-27 17:43:22 -07:00 |
|
tangxifan
|
a6fbbce33e
|
start developing the openfpga arch binding to vpr
|
2020-01-27 15:31:12 -07:00 |