tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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10cefebca8
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[engine] fixing bugs on using subtile index
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2022-08-23 11:00:23 -07:00 |
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tangxifan
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e0ae851e28
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[engine] correcting compilation errors due to vpr upgrade
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2022-08-17 16:25:12 -07:00 |
Tarachand Pagarani
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02e4ae9740
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allow bitstream setting on hard blocks
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2021-12-07 03:42:22 -08:00 |
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tangxifan
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0aec30bac6
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[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
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2021-04-19 15:53:33 -06:00 |
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tangxifan
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d877a02534
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[Tool] Patch the extended bitstream setting support on mode-select bits
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2021-03-10 21:28:09 -07:00 |
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tangxifan
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85640a7403
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[Tool] Extend bitstream setting to support mode bits overload from eblif file
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2021-03-10 20:45:48 -07:00 |
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tangxifan
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6a0f4f354f
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[Tool] Support superLUT circuit model in core engine
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2021-02-09 20:23:05 -07:00 |
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tangxifan
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0c409b5bcc
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[Tool] Add bitstream annotation support
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2021-02-01 20:49:36 -07:00 |
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tangxifan
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5be9e9b736
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[Tool] Adapted tools to support I/O in center grid
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2020-12-04 18:50:13 -07:00 |
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tangxifan
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4a2874b2bc
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[Tool] Refactor the codes for walking through io blocks
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2020-11-03 13:21:50 -07:00 |
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tangxifan
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62fd0947f5
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using a unified string to replace multi net names to save memory of bitstream database
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2020-07-08 16:28:20 -06:00 |
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tangxifan
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033c92c365
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precisely reserve memory for child blocks in bitstream manager
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2020-07-03 22:47:21 -06:00 |
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tangxifan
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46f038c829
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bug fix in grid config block allocation
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2020-07-03 20:46:04 -06:00 |
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tangxifan
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f040fc78a9
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now reserve blocks in bitstream manager can accurately capture the size
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2020-07-03 20:06:12 -06:00 |
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tangxifan
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2783fda344
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use index range instead of vector for block bitstream
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2020-07-03 11:42:38 -06:00 |
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tangxifan
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246b4d5ac6
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reserve block bits to save memory
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2020-07-02 21:52:32 -06:00 |
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tangxifan
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dee4be96af
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reserve all the input/output net storage in bitstream manager
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2020-07-02 19:17:34 -06:00 |
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tangxifan
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675a59ecb8
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Move fpga_bitstream to the libopenfpga library and add XML reader
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2020-06-20 18:25:17 -06:00 |
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tangxifan
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b91c30191a
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add input and output net echo in arch bitstream database
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2020-06-17 00:04:55 -06:00 |
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tangxifan
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19c0b57df6
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ignore invalid nets when decoding bitstream
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2020-06-16 22:26:36 -06:00 |
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tangxifan
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9d0e002532
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echo path in architecture bitstream database
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2020-06-16 21:29:45 -06:00 |
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tangxifan
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65df309419
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bug fixing for frame-based configuration protocol and rename some naming function to be generic
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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e601a648cc
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relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
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2020-03-27 19:07:34 -06:00 |
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tangxifan
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3807a940f4
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fixed critical bugs in bitstream generation and now we pass microbenchmarks
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2020-02-28 16:45:50 -07:00 |
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tangxifan
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410dcf6ab6
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debugged LUT bitstream
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2020-02-26 11:42:18 -07:00 |
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tangxifan
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759758421d
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found the bug in physical pb mode bits and fixed
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2020-02-25 23:45:49 -07:00 |
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tangxifan
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075264e3e3
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debugging LUT bitstream generation
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2020-02-25 23:29:16 -07:00 |
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tangxifan
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2c44c70557
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bring pb interconnection bitstream generation online
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2020-02-25 00:28:06 -07:00 |
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tangxifan
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04c69d30c2
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start adding grid bitstream builder. TODO: lut and interconnect bitstream decoding
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2020-02-24 19:38:02 -07:00 |