tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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6f09f5f7ad
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[FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank
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2021-09-05 21:25:58 -07:00 |
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tangxifan
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1085e468e2
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[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file
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2021-09-05 20:45:56 -07:00 |
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tangxifan
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b78f8bec16
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
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tangxifan
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5bcd559851
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[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
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2020-10-30 17:29:04 -06:00 |
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tangxifan
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0d77916041
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[Tool] Support multi-region frame-based configuration protocol
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2020-10-30 10:43:11 -06:00 |
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tangxifan
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987eccf586
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[Tool] Bug fix in multi-region memory bank; Basic test passed
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2020-10-29 16:26:45 -06:00 |
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tangxifan
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448e88645a
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[Tool] Support multiple memory banks in top-level module
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2020-10-29 12:42:03 -06:00 |
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tangxifan
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e0d7bcfa11
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[Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols
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2020-09-29 12:49:32 -06:00 |
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tangxifan
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e988e35f81
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[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
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2020-09-29 12:22:10 -06:00 |
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tangxifan
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8067a13346
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bug fix for memory bank due to encoding bl/wl addresses in fabric bitstream
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2020-07-03 15:56:20 -06:00 |
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tangxifan
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2a9377b3f4
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use encoded address in storage of fabric bitstream to save memory
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2020-07-03 15:12:29 -06:00 |
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tangxifan
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6ea857ae6c
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use fast method to inquire number of bits and blocks in bitstream databases
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2020-07-03 10:55:25 -06:00 |
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tangxifan
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7ca1a5bdc1
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Fabric bitstream now allocates vectors in conditions for memory efficiency
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2020-07-03 10:17:03 -06:00 |
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tangxifan
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9f19c36a89
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use char in fabric bitstream to save memory footprint
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2020-07-02 15:56:50 -06:00 |
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tangxifan
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b85af57971
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optimizing fabric bitsteream memory footprint
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2020-07-02 12:39:18 -06:00 |
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tangxifan
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3c10af7f2b
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bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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5368485bd6
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keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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0bee70bee6
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finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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51e1559352
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add fabric bitstream support for memory bank configuration protocol
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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8298bbff78
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bug fixed in the fabric bitstream for frame-based configurable memories.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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cff5b5cfc1
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break the configuration testbench. This commit is to spot which modification leads to the problem
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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85921dcc05
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add fabric bitstream builder for frame-based configuration protocol
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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4a0e1cd908
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add fabric bitstream data structure and deploy it to Verilog testbench generation
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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a26d31b87f
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make write bitstream online
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2020-02-26 11:09:23 -07:00 |
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tangxifan
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86c7c24701
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add fabric bitstream generation online
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2020-02-23 20:58:17 -07:00 |