tangxifan
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460fef5807
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[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
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2020-09-20 12:58:55 -06:00 |
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tangxifan
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1ad6e8292a
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move constants from verilog domain to common so that FPGA-SPICE can share
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2020-07-05 11:39:46 -06:00 |
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tangxifan
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5c5a044c68
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add architecture decoder (for frame-based config memory) to Verilog writer
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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69306faf22
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add a new include netlist for all the fabric-related netlists
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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65c81e14b2
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add simulation ini file writer
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2020-02-27 18:01:47 -07:00 |
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tangxifan
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e9adb4fdbc
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add preconfig top module Verilog generation
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2020-02-26 20:38:01 -07:00 |
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tangxifan
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e37ac8a098
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add grid module Verilog writer
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2020-02-16 16:04:41 -07:00 |
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tangxifan
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c20caa1fa3
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routing module Verilog writer is online
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2020-02-16 14:47:54 -07:00 |
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tangxifan
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105ccabecc
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adapt memroy writer for verilog
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2020-02-16 12:41:43 -07:00 |
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tangxifan
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c9d8120ae0
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adapt Verilog mux writer
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2020-02-16 12:35:41 -07:00 |
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tangxifan
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4cb61e2138
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bring preprocessing flag Verilog netlists online
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2020-02-16 00:03:24 -07:00 |
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tangxifan
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622c7826d1
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start transplanting fpga_verilog
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2020-02-15 15:03:00 -07:00 |