tangxifan
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de44e8c9d1
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[Test] Bug fix for github actions
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2020-11-23 20:24:18 -07:00 |
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tangxifan
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a95ddef90d
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[Test] Bug fix in calling scripts for Github Actions
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2020-11-23 20:22:59 -07:00 |
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tangxifan
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f2b6655550
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[Test] Start porting to Github Actions with build test
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2020-11-23 20:19:44 -07:00 |
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tangxifan
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c82f01b3ab
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[Tool] Use conditional operator in signal initialization to eliminate all the warning messages
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2020-11-23 15:50:23 -07:00 |
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tangxifan
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b857135f4e
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[Doc] Add clarification about which cells are applicable for signal initialization
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2020-11-23 15:19:15 -07:00 |
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tangxifan
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2b9a97729e
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[Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models
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2020-11-23 15:09:47 -07:00 |
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tangxifan
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e644545f21
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[Doc] Remove signal initialization for select ports of MUXes and Pass-gates; Use urandom to generate just-fit random vectors
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2020-11-23 15:02:06 -07:00 |
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tangxifan
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6ba02f35ca
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Merge pull request #130 from antmicro/rr_graph_load_fix
Fix for rr graph loading by VPR
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2020-11-23 09:31:29 -07:00 |
Maciej Kurc
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3d38e76c8f
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Disabled printing segment ids for non-channel nodes.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2020-11-23 17:07:28 +01:00 |
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Maciej Kurc
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b6728cf2d9
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Added loading rr node segment indices
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2020-11-23 14:53:50 +01:00 |
Laboratory for Nano Integrated Systems (LNIS)
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b78803a6bb
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Merge pull request #129 from LNIS-Projects/dev
Generate Signal Initialization in Verilog Testbenches rather than HDL netlists
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2020-11-22 21:48:22 -07:00 |
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tangxifan
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fd80cacaa3
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[Flow] Add example script for behaviorial verilog generation
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2020-11-22 21:14:10 -07:00 |
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tangxifan
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617f7e3062
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[Flow] disable signal initialization for behavioral verilog generation
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2020-11-22 21:13:22 -07:00 |
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tangxifan
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5eb04e6fff
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[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
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2020-11-22 20:53:32 -07:00 |
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tangxifan
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fd0e6814ea
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[Doc] Update documentation about the pre-processing flags
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2020-11-22 20:33:15 -07:00 |
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tangxifan
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3b2a4c5387
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[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
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2020-11-22 20:25:03 -07:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
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348872f8a4
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[Flow] Adapt OpenFPGA shell script for the preprocessing flag option changes
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2020-11-22 16:12:28 -07:00 |
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tangxifan
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57a24570f5
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[Tool] Move icarus and signal initialization options to testbench generator
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2020-11-22 16:01:31 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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a00752938b
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Merge pull request #127 from LNIS-Projects/dev
Bug fix for global clock port using physical tile pins
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2020-11-17 15:56:08 -07:00 |
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tangxifan
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845436fa71
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[Test] Add sequential benchmark for global tile clock test case
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2020-11-17 14:34:54 -07:00 |
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tangxifan
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91b0dbbaa2
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[Script] Add example openfpga shell run script when using global tile clocks
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2020-11-17 14:33:12 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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3a80af3408
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Merge pull request #126 from LNIS-Projects/dev
Multiple Bug Fixes
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2020-11-13 16:44:58 -07:00 |
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tangxifan
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3f91b8433e
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[Tool] Change the i/o numbering to the clockwise sequence
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2020-11-13 15:00:25 -07:00 |
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tangxifan
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088198c861
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[Tool] enhance error checking in fabric key parser
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2020-11-13 10:56:00 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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c05de43927
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Merge pull request #124 from LNIS-Projects/dev
Add readthedoc Setting File
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2020-11-12 21:12:05 -07:00 |
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tangxifan
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cb025e982f
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[Doc] Add readthedoc setting file
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2020-11-12 19:43:43 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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32da241edd
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Merge pull request #123 from LNIS-Projects/dev
Add Illustrative Example to Documentation to Explain the Difference on Global Port Definitions between Circuit Model and Tile Annotation
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2020-11-12 10:23:33 -07:00 |
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tangxifan
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f6126d1ed6
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[Doc] Add illustrative example to diff between global ports definitions
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2020-11-12 09:24:39 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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2af49c245f
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Merge pull request #122 from LNIS-Projects/dev
Support Global Port Definition for Physical Tile Ports
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2020-11-11 16:16:32 -07:00 |
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tangxifan
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372fb261fd
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[Tool] Extend the support on global tile port for I/O tiles
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2020-11-11 15:09:40 -07:00 |
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tangxifan
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bc43c876b0
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[Doc] Update documentation for the rules in global port definition for tile ports
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2020-11-11 14:10:11 -07:00 |
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tangxifan
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e959821813
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[Tool] Enhance internal check functions for tile annotation
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2020-11-11 13:59:24 -07:00 |
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tangxifan
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e627b6dd5d
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[Tool] Enhance port attribute checks in tile annotation data structure
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2020-11-11 13:41:05 -07:00 |
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tangxifan
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9cbc374b33
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[Tool] Add check codes for tile annotation
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2020-11-11 12:03:13 -07:00 |
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tangxifan
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81e56d45d6
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[Tool] Update FPGA-SDC to use the new data structure for global ports
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2020-11-10 21:17:17 -07:00 |
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tangxifan
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2c269c532a
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[Doc] Update doc for the global port definition using physical tile port
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2020-11-10 20:48:28 -07:00 |
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tangxifan
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4dc0fb81c5
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[Tool] Bug fix for clang compilation error
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2020-11-10 20:32:58 -07:00 |
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tangxifan
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c61ec5a8b8
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[Tool] Bug fix for defining global ports from tiles
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2020-11-10 20:31:14 -07:00 |
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tangxifan
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05f5ce38ea
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[Test] Deploy new test to CI
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2020-11-10 20:31:03 -07:00 |
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tangxifan
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485258a9ea
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[Test] Add test case for global clock from tiles
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2020-11-10 19:24:25 -07:00 |
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tangxifan
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f29916921a
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[Arch] Add openfpga arch for using global clocks from tiles
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2020-11-10 19:20:08 -07:00 |
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tangxifan
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a6531d9e8d
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[Arch] Add k4 arch using global clock from tile port (with zero fc)
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2020-11-10 19:17:34 -07:00 |
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tangxifan
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dcb50e4f19
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[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
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tangxifan
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cbb1545ee3
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[Tool] Add connection builder for tile global ports to top-level module
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2020-11-10 16:59:00 -07:00 |
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tangxifan
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67af145455
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[Tool] Add XML writer for tile annotation
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2020-11-10 14:51:46 -07:00 |
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tangxifan
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75ce4b5e25
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[Arch] Fine tune example arch
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2020-11-10 14:38:47 -07:00 |
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tangxifan
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6fbdbe68ae
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[Tool] Add tile annotation parser
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2020-11-10 14:32:24 -07:00 |
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tangxifan
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d127304760
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[Arch] Update sample arch using local clock from physical tile ports
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2020-11-10 14:31:58 -07:00 |
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tangxifan
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4ca2a129c2
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[Arch] Add an sample architecture where global clock port is defined from tile ports
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2020-11-10 11:47:03 -07:00 |