riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Test] Deploy new test to CI

This commit is contained in:
tangxifan 2020-11-10 20:31:03 -07:00
parent 485258a9ea
commit 05f5ce38ea
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
.travis/basic_reg_test.sh
View File

@ -106,4 +106,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top
echo -e "Testing tiles with pins only on bottom and right sides";
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs
echo -e "Testing global port definition from tiles";
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs
end_section "OpenFPGA.TaskTun"