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7079 Commits

Author SHA1 Message Date
tangxifan b072e3d163
Merge pull request #1527 from lnis-uofu/dependabot/submodules/yosys-8649e30 
Bump yosys from `8bd681a` to `8649e30`
 2024-01-22 15:29:17 -08:00
tangxifan 156e6fa207
Merge branch 'master' into dependabot/submodules/yosys-8649e30 2024-01-22 11:59:48 -08:00
tangxifan ecfae3b911
Merge pull request #1529 from coolbreeze413/remove-integrated-quicklogic-plugins-code-in-yosys 
Fix quicklogic tests by removing integrated quicklogic plugins code in yosys
 2024-01-22 11:59:21 -08:00
coolbreeze413 5c45291763 Update build step to remove quicklogic-integrated-plugins-code, Update yosys to latest bump-version 2024-01-22 23:16:32 +05:30
dependabot[bot] 92ff9b0fa0
Bump yosys from `8bd681a` to `8649e30` 
Bumps [yosys](https://github.com/YosysHQ/yosys) from `8bd681a` to `8649e30`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](8bd681acfc...8649e30668)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2024-01-22 07:10:29 +00:00
tangxifan d2fa9aca09
Merge pull request #1516 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2024-01-12 15:54:57 -08:00
github-actions[bot] 0346b01d4f Updated Patch Count 2024-01-12 23:53:33 +00:00
tangxifan de1b68cc86
Merge pull request #1515 from lnis-uofu/xt_pbpin 
[core] fixed a bug where pb pin fixup may fail when subtile capacities are not same
 2024-01-12 15:53:02 -08:00
tangxifan 59deb97d5d [core] code format 2024-01-12 14:17:10 -08:00
tangxifan f1e3d53da6 [core] fixed a bug where pb pin fixup may fail when subtile capacities are not same 2024-01-12 14:16:07 -08:00
tangxifan e1ee5d5c7a
Merge pull request #1491 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-12-12 18:03:36 -08:00
github-actions[bot] 56905da77e Updated Patch Count 2023-12-13 00:02:13 +00:00
tangxifan 26e679ae82
Merge pull request #1490 from lnis-uofu/xt_flow 
Update openfpga flow to allow custom default tool path configuration
 2023-12-12 16:01:43 -08:00
tangxifan 073161f523 [doc] add new option 2023-12-12 14:20:51 -08:00
tangxifan 2bd60dad11 [script] now timing extraction focus on the last found results 2023-12-12 14:10:13 -08:00
tangxifan 592e2e310c [script] typo 2023-12-12 13:45:23 -08:00
tangxifan b182b47d0b [test] use a timing-focus tool path for a testcase 2023-12-12 13:28:35 -08:00
tangxifan c5cc05a9f5 [script] add a new example default tool path config with a focus on timing 2023-12-12 13:22:50 -08:00
tangxifan f689ef7654 [script] format 2023-12-12 13:15:03 -08:00
tangxifan 4c0f6e2273 [script] syntax 2023-12-12 13:14:47 -08:00
tangxifan e753e6d22c [script] syntax 2023-12-12 13:13:51 -08:00
tangxifan d9db78ac30 [script] now run fpga task has a new option ``default_tool_path`` 2023-12-12 13:11:48 -08:00
tangxifan 1a4aaaf759 [script] update openfpga flow to support args for default tool path 2023-12-12 10:00:50 -08:00
tangxifan a7b22163a8 [script] fixe the mismatch on keywords against latest vpr 2023-12-12 09:52:42 -08:00
tangxifan d6fe414cd1
Merge pull request #1485 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-12-10 19:45:28 -08:00
github-actions[bot] 8def72ee01 Updated Patch Count 2023-12-10 00:02:47 +00:00
tangxifan b494740781
Merge pull request #1484 from lnis-uofu/xt_hotfix 
Support VCS simulator for QL memory bank in full testbench
 2023-12-08 16:35:47 -08:00
tangxifan 2879bf2e6e [doc] add new option 2023-12-08 13:56:46 -08:00
tangxifan 5c839c1858 [test] debug 2023-12-08 13:52:52 -08:00
tangxifan 6a5df804b9 [test] add new testcase to reg test 2023-12-08 13:46:54 -08:00
tangxifan 99f1c5493c [test] add a new testcase to support vcs 2023-12-08 13:45:23 -08:00
tangxifan bacd845139 [core] code format 2023-12-08 13:41:41 -08:00
tangxifan 5e181cbe72 [core] add a new option for simulator type to verilog full testbench generator 2023-12-08 13:07:25 -08:00
tangxifan 0e945d6e71 [core] fix a bug in ql memory bank tb where VCS failed 2023-12-08 11:36:54 -08:00
tangxifan 8fe9811326
Merge pull request #1482 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-12-06 16:06:08 -08:00
github-actions[bot] 8f13674e80 Updated Patch Count 2023-12-07 00:02:28 +00:00
tangxifan f6caa148e3
Merge pull request #1481 from lnis-uofu/xt_ci 
[ci] format labeler
 2023-12-06 12:41:18 -08:00
tangxifan 98c9290636 [ci] format labeler 2023-12-06 12:35:45 -08:00
tangxifan 60b3df0111
Merge pull request #1476 from lnis-uofu/tangxifan-patch-2 
Update labeler.yml to use v4 version. Since v5 introduces breaking ch…
 2023-12-06 11:15:13 -08:00
tangxifan ebe17baf7c Merge branch 'tangxifan-patch-2' of github.com:lnis-uofu/OpenFPGA into tangxifan-patch-2 2023-12-06 11:12:35 -08:00
tangxifan 7cc43dea4a [ci] debugging 2023-12-06 11:11:55 -08:00
tangxifan 4fd71ed34a
Merge branch 'master' into tangxifan-patch-2 2023-12-05 21:39:58 -08:00
tangxifan 33f0f0feed [ci] typo 2023-12-05 21:09:43 -08:00
tangxifan 77d55ae0b4
Merge pull request #1457 from lnis-uofu/repack_debug 
Repack debug
 2023-12-05 18:03:46 -08:00
tangxifan 7a41aaf19b [ci] typo 2023-12-05 17:55:04 -08:00
tangxifan 95703fd9e6 [ci] use checkout in labeler; following the latst documentation https://github.com/actions/labeler#using-configuration-path-input-together-with-the-actionscheckout-action 2023-12-05 17:53:22 -08:00
tangxifan e28b714305
Merge branch 'master' into repack_debug 2023-12-05 16:14:35 -08:00
tangxifan 1012059227
Merge pull request #1475 from lnis-uofu/revert-1473-dependabot/submodules/yosys-2ffea67 
Revert "Bump yosys from `8bd681a` to `2ffea67`"
 2023-12-05 16:13:12 -08:00
tangxifan ce4f7d0719
Update labeler.yml to use v4 version. Since v5 introduces breaking changes, which takes time to adapt 2023-12-05 10:56:27 -08:00
tangxifan 0a1780b15a
Revert "Bump yosys from `8bd681a` to `2ffea67`" 2023-12-05 10:49:19 -08:00