Merge pull request #1484 from lnis-uofu/xt_hotfix
Support VCS simulator for QL memory bank in full testbench
This commit is contained in:
tangxifan
GitHub
commit
b494740781
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@ -61,6 +61,10 @@ write_full_testbench
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The bitstream file to be loaded to the full testbench, which should be in the same file format that OpenFPGA can outputs (See detailes in :ref:`file_formats_fabric_bitstream_plain_text`). For example, ``--bitstream and2.bit``
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.. option:: --simulator <string>
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Specify the type of simulator which the full testbench will be used for. Currently support ``iverilog`` | ``vcs``. By default, assume the simulator is iverilog. For example, ``--simulator iverilog``. For different types of simulator, some syntax in the testbench may differ to help fast convergence.
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.. option:: --fabric_netlist_file_path <string>
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Specify the fabric Verilog file if they are not in the same directory as the testbenches to be generated. If not specified, OpenFPGA will assume that the fabric netlists are the in the same directory as testbenches and assign default names. For example, ``--file /temp/fabric/fabric_netlists.v``
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@ -104,6 +104,11 @@ ShellCommandId add_write_full_testbench_command_template(
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"bitstream", true, "specify the bitstream to be loaded in the testbench");
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shell_cmd.set_option_require_value(bitstream_opt, openfpga::OPT_STRING);
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/* add an option '--simulator'*/
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CommandOptionId sim_opt = shell_cmd.add_option(
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"simulator", false, "specify the simulator to be used for the testbench");
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shell_cmd.set_option_require_value(sim_opt, openfpga::OPT_STRING);
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/* add an option '--fabric_netlist_file_path'*/
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CommandOptionId fabric_netlist_opt =
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shell_cmd.add_option("fabric_netlist_file_path", false,
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@ -74,6 +74,7 @@ int write_full_testbench_template(const T& openfpga_ctx, const Command& cmd,
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const CommandContext& cmd_context) {
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CommandOptionId opt_output_dir = cmd.option("file");
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CommandOptionId opt_bitstream = cmd.option("bitstream");
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CommandOptionId opt_sim = cmd.option("simulator");
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CommandOptionId opt_dut_module = cmd.option("dut_module");
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CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
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CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
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@ -132,6 +133,11 @@ int write_full_testbench_template(const T& openfpga_ctx, const Command& cmd,
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read_xml_bus_group(cmd_context.option_value(cmd, opt_bgf).c_str());
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}
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/* Configure the simulator */
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if (true == cmd_context.option_enable(cmd, opt_sim)) {
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options.set_simulator_type(cmd_context.option_value(cmd, opt_sim));
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}
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return fpga_verilog_full_testbench(
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openfpga_ctx.module_graph(), openfpga_ctx.bitstream_manager(),
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openfpga_ctx.fabric_bitstream(), openfpga_ctx.blwl_shift_register_banks(),
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@ -30,7 +30,10 @@ VerilogTestbenchOption::VerilogTestbenchOption() {
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time_unit_ = 1E-3;
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time_stamp_ = true;
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use_relative_path_ = false;
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simulator_type_ = e_simulator_type::IVERILOG;
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verbose_output_ = false;
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SIMULATOR_TYPE_STRING_ = {{"iverilog", "vcs"}};
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}
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/**************************************************
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@ -107,6 +110,11 @@ bool VerilogTestbenchOption::use_relative_path() const {
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bool VerilogTestbenchOption::verbose_output() const { return verbose_output_; }
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VerilogTestbenchOption::e_simulator_type
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VerilogTestbenchOption::simulator_type() const {
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return simulator_type_;
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}
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/******************************************************************************
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* Private Mutators
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******************************************************************************/
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@ -259,4 +267,52 @@ void VerilogTestbenchOption::set_verbose_output(const bool& enabled) {
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verbose_output_ = enabled;
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}
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int VerilogTestbenchOption::set_simulator_type(const std::string& value) {
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simulator_type_ = str2simulator_type(value);
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return valid_simulator_type(simulator_type_);
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}
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std::string VerilogTestbenchOption::simulator_type_all2str() const {
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std::string full_types = "[";
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for (int itype = size_t(VerilogTestbenchOption::e_simulator_type::IVERILOG);
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itype != size_t(VerilogTestbenchOption::e_simulator_type::NUM_TYPES);
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++itype) {
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full_types += std::string(SIMULATOR_TYPE_STRING_[itype]) + std::string("|");
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}
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full_types.pop_back();
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full_types += "]";
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return full_types;
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}
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VerilogTestbenchOption::e_simulator_type
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VerilogTestbenchOption::str2simulator_type(const std::string& type_str,
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const bool& verbose) const {
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for (int itype = size_t(VerilogTestbenchOption::e_simulator_type::IVERILOG);
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itype != size_t(VerilogTestbenchOption::e_simulator_type::NUM_TYPES);
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++itype) {
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if (type_str == std::string(SIMULATOR_TYPE_STRING_[itype])) {
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return static_cast<VerilogTestbenchOption::e_simulator_type>(itype);
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}
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}
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VTR_LOGV_ERROR(verbose, "Invalid simulator type! Expect %s\n",
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simulator_type_all2str().c_str());
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return VerilogTestbenchOption::e_simulator_type::NUM_TYPES;
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}
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std::string VerilogTestbenchOption::simulator_type2str(
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const VerilogTestbenchOption::e_simulator_type& sim_type,
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const bool& verbose) const {
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if (!valid_simulator_type(sim_type)) {
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VTR_LOGV_ERROR(verbose, "Invalid type for simulator! Expect %s\n",
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simulator_type_all2str().c_str());
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return std::string();
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}
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return std::string(SIMULATOR_TYPE_STRING_[size_t(sim_type)]);
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}
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bool VerilogTestbenchOption::valid_simulator_type(
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const VerilogTestbenchOption::e_simulator_type& sim_type) const {
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return sim_type != VerilogTestbenchOption::e_simulator_type::NUM_TYPES;
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}
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} /* end namespace openfpga */
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@ -31,6 +31,16 @@ constexpr std::array<const char*, NUM_EMBEDDED_BITSTREAM_HDL_TYPES + 1>
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*
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*******************************************************************/
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class VerilogTestbenchOption {
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/* Public types */
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public:
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/* Embedded bitstream code style */
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enum class e_simulator_type { IVERILOG = 0, VCS, NUM_TYPES };
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/* Constants */
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private:
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/* String version of simulator types. Used for debugging/error messages */
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std::array<const char*, size_t(e_simulator_type::NUM_TYPES)>
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SIMULATOR_TYPE_STRING_;
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public: /* Public constructor */
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/* Set default options */
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VerilogTestbenchOption();
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@ -56,6 +66,7 @@ class VerilogTestbenchOption {
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bool time_stamp() const;
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bool use_relative_path() const;
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bool verbose_output() const;
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e_simulator_type simulator_type() const;
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public: /* Public validator */
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bool validate() const;
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@ -95,6 +106,18 @@ class VerilogTestbenchOption {
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void set_use_relative_path(const bool& enabled);
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void set_verbose_output(const bool& enabled);
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/* @brief Create the simulator type by parsing a given string. Return error
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* when failed */
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int set_simulator_type(const std::string& value);
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private: /* Private utility and validators */
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e_simulator_type str2simulator_type(const std::string& value,
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const bool& verbose = false) const;
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std::string simulator_type2str(const e_simulator_type& sim_type,
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const bool& verbose = false) const;
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std::string simulator_type_all2str() const;
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bool valid_simulator_type(const e_simulator_type& sim_type) const;
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private: /* Internal Data */
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std::string output_directory_;
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std::string top_module_;
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@ -111,6 +134,7 @@ class VerilogTestbenchOption {
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bool include_signal_init_;
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e_verilog_default_net_type default_net_type_;
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e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_;
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e_simulator_type simulator_type_;
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float time_unit_;
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bool time_stamp_;
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bool use_relative_path_;
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@ -1423,7 +1423,8 @@ static int print_verilog_top_testbench_configuration_protocol_stimulus(
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const ModuleId& top_module, const bool& fast_configuration,
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const bool& bit_value_to_skip, const FabricBitstream& fabric_bitstream,
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const MemoryBankShiftRegisterBanks& blwl_sr_banks,
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const float& prog_clock_period, const float& timescale) {
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const float& prog_clock_period, const float& timescale,
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const VerilogTestbenchOption::e_simulator_type sim_type) {
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/* Validate the file stream */
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valid_file_stream(fp);
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@ -1437,7 +1438,7 @@ static int print_verilog_top_testbench_configuration_protocol_stimulus(
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return print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus(
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fp, config_protocol, sim_settings, module_manager, top_module,
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fast_configuration, bit_value_to_skip, fabric_bitstream, blwl_sr_banks,
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prog_clock_period, timescale);
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prog_clock_period, timescale, sim_type);
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break;
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case CONFIG_MEM_MEMORY_BANK:
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case CONFIG_MEM_FRAME_BASED: {
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@ -2564,7 +2565,7 @@ int print_verilog_full_testbench(
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status = print_verilog_top_testbench_configuration_protocol_stimulus(
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fp, config_protocol, simulation_parameters, module_manager, core_module,
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fast_configuration, bit_value_to_skip, fabric_bitstream, blwl_sr_banks,
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prog_clock_period, VERILOG_SIM_TIMESCALE);
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prog_clock_period, VERILOG_SIM_TIMESCALE, options.simulator_type());
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if (status == CMD_EXEC_FATAL_ERROR) {
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return status;
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@ -317,7 +317,8 @@ void print_verilog_top_testbench_global_shift_register_clock_ports_stimuli(
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static void
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print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generator(
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std::fstream& fp, const BasicPort& start_sr_port,
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const BasicPort& sr_clock_port, const float& sr_clock_period) {
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const BasicPort& sr_clock_port, const float& sr_clock_period,
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const VerilogTestbenchOption::e_simulator_type sim_type) {
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/* Validate the file stream */
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valid_file_stream(fp);
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@ -345,10 +346,14 @@ print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generat
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fp << "end";
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fp << std::endl;
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fp << "\t";
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fp << generate_verilog_port_constant_values(
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sr_clock_port, std::vector<size_t>(sr_clock_port.get_width(), 0), true);
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fp << ";" << std::endl;
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// The following code does not work when using Synopsys VCS. Comment them out.
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// See if iverilog is fine or not
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if (sim_type == VerilogTestbenchOption::e_simulator_type::IVERILOG) {
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fp << "\t";
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fp << generate_verilog_port_constant_values(
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sr_clock_port, std::vector<size_t>(sr_clock_port.get_width(), 0), true);
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fp << ";" << std::endl;
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}
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fp << "end";
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fp << std::endl;
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@ -453,7 +458,8 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus(
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const ModuleId& top_module, const bool& fast_configuration,
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const bool& bit_value_to_skip, const FabricBitstream& fabric_bitstream,
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const MemoryBankShiftRegisterBanks& blwl_sr_banks,
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const float& prog_clock_period, const float& timescale) {
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const float& prog_clock_period, const float& timescale,
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const VerilogTestbenchOption::e_simulator_type sim_type) {
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ModulePortId en_port_id = module_manager.find_module_port(
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top_module, std::string(DECODER_ENABLE_PORT_NAME));
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BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1);
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@ -531,7 +537,8 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus(
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print_verilog_comment(
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fp, "----- BL Shift register virtual clock generator -----");
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print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generator(
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fp, start_bl_sr_port, virtual_bl_sr_clock_port, bl_sr_clock_period);
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fp, start_bl_sr_port, virtual_bl_sr_clock_port, bl_sr_clock_period,
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sim_type);
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print_verilog_comment(fp,
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"----- BL Shift register clock generator -----");
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@ -543,7 +550,8 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus(
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print_verilog_comment(
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fp, "----- WL Shift register virtual clock generator -----");
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print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generator(
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fp, start_wl_sr_port, virtual_wl_sr_clock_port, wl_sr_clock_period);
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fp, start_wl_sr_port, virtual_wl_sr_clock_port, wl_sr_clock_period,
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sim_type);
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print_verilog_comment(fp,
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"----- WL Shift register clock generator -----");
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print_verilog_full_testbench_ql_memory_bank_shift_register_clock_generator(
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@ -54,7 +54,8 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus(
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const ModuleId& top_module, const bool& fast_configuration,
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const bool& bit_value_to_skip, const FabricBitstream& fabric_bitstream,
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const MemoryBankShiftRegisterBanks& blwl_sr_banks,
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const float& prog_clock_period, const float& timescale);
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const float& prog_clock_period, const float& timescale,
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const VerilogTestbenchOption::e_simulator_type sim_type);
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/**
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* @brief Print stimulus for a FPGA fabric with a memory bank configuration
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@ -0,0 +1,71 @@
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# Run VPR for the 'and' design
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal ${OPENFPGA_VPR_DEVICE_LAYOUT}
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing #--verbose
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# Write the fabric hierarchy of module graph to a file
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# This is used by hierarchical PnR flows
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write_fabric_hierarchy --file ./fabric_hierarchy.txt
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# Repack the netlist to physical pbs
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# This must be done before bitstream generator and testbench generation
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# Strongly recommend it is done after all the fix-up have been applied
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repack #--verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
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# Build fabric-dependent bitstream
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build_fabric_bitstream --verbose
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# Write fabric-dependent bitstream
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write_fabric_bitstream --file fabric_bitstream.bit --format plain_text ${OPENFPGA_FAST_CONFIGURATION}
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# Write the Verilog netlist for FPGA fabric
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# - Enable the use of explicit port mapping in Verilog netlist
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write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
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# Write the Verilog testbench for FPGA fabric
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# - We suggest the use of same output directory as fabric Verilog netlists
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# - Must specify the reference benchmark file if you want to output any testbenches
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# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
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# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
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# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION} ${OPENFPGA_SIMULATOR}
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# Write the SDC files for PnR backend
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# - Turn on every options here
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write_pnr_sdc --file ./SDC
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# Write SDC to disable timing for configure ports
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write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
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# Write the SDC to run timing analysis for a mapped FPGA fabric
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write_analysis_sdc --file ./SDC_analysis
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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@ -83,6 +83,9 @@ run-task basic_tests/full_testbench/ql_memory_bank_shift_register $@
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run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr $@
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run-task basic_tests/full_testbench/ql_memory_bank_shift_register_multi_chain $@
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echo -e "Testing simulator support";
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run-task basic_tests/full_testbench/ql_memory_bank_shift_register_vcs $@
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echo -e "Testing testbenches without self checking features";
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run-task basic_tests/full_testbench/full_testbench_without_self_checking $@
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run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking $@
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@ -0,0 +1,47 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=yosys_vpr
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_simulator_support_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_shift_register_sim_openfpga.xml
|
||||
|
||||
openfpga_vpr_device_layout=
|
||||
openfpga_fast_configuration=
|
||||
openfpga_simulator=--simulator vcs
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
|
||||
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench_read_verilog_options_common = -nolatches
|
||||
bench0_top = and2
|
||||
bench0_chan_width = 300
|
||||
|
||||
bench1_top = or2
|
||||
bench1_chan_width = 300
|
||||
|
||||
bench2_top = and2_latch
|
||||
bench2_chan_width = 300
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
#end_flow_with_test=
|
||||
Loading…
Reference in New Issue