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Merge pull request #1515 from lnis-uofu/xt_pbpin 

[core] fixed a bug where pb pin fixup may fail when subtile capacities are not same
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tangxifan 2024-01-12 15:53:02 -08:00 committed by GitHub
parent e1ee5d5c7a 59deb97d5d
commit de1b68cc86
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1 changed files with 2 additions and 2 deletions
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openfpga/src/base/openfpga_pb_pin_fixup.cpp
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@ -47,8 +47,8 @@ static void update_cluster_pin_with_post_routing_results(
* here z offset is the location in the multiple-logic-tile tile Get
* physical pin does not consider THIS!!!!
*/
int physical_pin = z * logical_block->pb_type->num_pins +
get_physical_pin(physical_tile, logical_block, j);
int physical_pin =
get_physical_pin_at_sub_tile_location(physical_tile, logical_block, z, j);
auto pin_class = physical_tile->pin_class[physical_pin];
auto class_inf = physical_tile->class_inf[pin_class];