tangxifan
|
b035b4c87f
|
debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
|
2020-02-21 12:16:50 -07:00 |
|
tangxifan
|
c6c3ef71f3
|
adapt all the Verilog submodule writers and bring it onlien
|
2020-02-16 13:35:18 -07:00 |
|
tangxifan
|
a88c4bc954
|
add decode utils to libopenfpga and adapt local decoder writer in Verilog
|
2020-02-16 12:21:59 -07:00 |
|
tangxifan
|
622c7826d1
|
start transplanting fpga_verilog
|
2020-02-15 15:03:00 -07:00 |
|
tangxifan
|
59c13550e0
|
add direct annotation with inter-column/row syntax
|
2020-02-14 17:40:59 -07:00 |
|
tangxifan
|
df3ae60954
|
add default configurable memory model set-up when reading openfpga architecture XML
|
2020-02-12 15:19:40 -07:00 |
|
tangxifan
|
99f5a86b49
|
bug fixed for routing annotation and routing net fix-up
|
2020-02-06 12:54:55 -07:00 |
|
tangxifan
|
87f1ca1151
|
add naming fix-up report generation
|
2020-01-29 18:56:47 -07:00 |
|
tangxifan
|
24b180b298
|
change the mode bit storage in annotation data structure from string to vector of integers
|
2020-01-29 11:59:20 -07:00 |
|
tangxifan
|
df056f5d70
|
openfpga shell will stay in interactive mode after executing a script
|
2020-01-27 17:56:24 -07:00 |
|
tangxifan
|
5ecb771673
|
debugging the annotation to physical mode of pb_types
|
2020-01-27 17:43:22 -07:00 |
|
tangxifan
|
7d4b07421d
|
finish XML parser and writer for pb_type annotation
|
2020-01-26 15:54:49 -07:00 |
|
tangxifan
|
1cba141dd0
|
add pb parser and support XML parsing for pb type name in full hiearchy
|
2020-01-26 11:52:58 -07:00 |
|
tangxifan
|
cd3565cf53
|
complete the XML parser for pb_type annotation
|
2020-01-26 10:56:57 -07:00 |
|
tangxifan
|
a9f03ce21b
|
add XML attribute parsing for physical and operating pb_type annotation
|
2020-01-26 10:19:47 -07:00 |
|
tangxifan
|
bafd866cfc
|
start developing XML parser for pb_type annotation
|
2020-01-25 21:19:08 -07:00 |
|
tangxifan
|
b6f96e5a8f
|
add method functions to pb_type annotation
|
2020-01-25 20:46:21 -07:00 |
|
tangxifan
|
9b4b6ae083
|
rename pb_annotation and move it to openfpga namespace
|
2020-01-25 18:17:00 -07:00 |
|
tangxifan
|
f834954698
|
start developing the pb_type annotation
|
2020-01-25 18:14:38 -07:00 |
|
tangxifan
|
b4f4bf62a2
|
add comments to sample arch
|
2020-01-25 17:42:24 -07:00 |
|
tangxifan
|
7feeee8c0e
|
add full syntax to sample_arch.xml about the physical pb_type binding
|
2020-01-25 17:38:06 -07:00 |
|
tangxifan
|
b641ae15d3
|
add command dependency in shell execution
|
2020-01-24 16:46:39 -07:00 |
|
tangxifan
|
655f84b00e
|
add write_openfpga_arch command to openfpga shell
|
2020-01-23 20:58:15 -07:00 |
|
tangxifan
|
a03f8aa346
|
add profiling for read arch
|
2020-01-23 20:12:30 -07:00 |
|
tangxifan
|
cdb3b6de46
|
add read_openfpga_arch to OpenFPGA shell
|
2020-01-23 19:10:53 -07:00 |
|
tangxifan
|
e69aa5ba30
|
change type casting for vpr macro
|
2020-01-23 14:57:53 -07:00 |
|
tangxifan
|
26e6c4012f
|
add const context function execution for shell
|
2020-01-23 14:50:03 -07:00 |
|
tangxifan
|
523f9ac391
|
start implement openfpga shell and use vpr as a macro
|
2020-01-22 20:20:10 -07:00 |
|
tangxifan
|
e983966a08
|
add macro function support to openfpga shell and update unit test
|
2020-01-22 19:30:36 -07:00 |
|
tangxifan
|
558f0bb1bd
|
bug fixing in shell echo messages and add a test script
|
2020-01-22 17:11:24 -07:00 |
|
tangxifan
|
bb8ef9614f
|
change to namespace openfpga and bug fixed to avoid easy crash due to wrong options
|
2020-01-22 16:49:32 -07:00 |
|
tangxifan
|
f8c5c1a117
|
update shell with new function binding strategy and new help desk print-out
|
2020-01-22 16:05:14 -07:00 |
|
tangxifan
|
7073e4d082
|
add shell unit test
|
2020-01-21 22:59:53 -07:00 |
|
tangxifan
|
4f26e2519f
|
add shell interface and command execution
|
2020-01-21 20:46:24 -07:00 |
|
tangxifan
|
363ab382e5
|
add shell data structure
|
2020-01-21 17:24:49 -07:00 |
|
tangxifan
|
b53897b838
|
add how-to-use for command data structure
|
2020-01-20 22:53:11 -07:00 |
|
tangxifan
|
7a5b36fe52
|
Add echo command and unit test for command parser
|
2020-01-20 20:31:16 -07:00 |
|
tangxifan
|
3ae80a192f
|
add command echo functionality for mini shell
|
2020-01-20 19:42:43 -07:00 |
|
tangxifan
|
acdb3818c2
|
start developing mini shell for open fpga
|
2020-01-20 18:14:24 -07:00 |
|
tangxifan
|
16752b7e39
|
update on sample arch
|
2020-01-20 12:42:08 -07:00 |
|
tangxifan
|
07994d424c
|
add XML parser and writer for direct connection
|
2020-01-19 15:00:19 -07:00 |
|
tangxifan
|
10336cbe67
|
add XML parser and writer for routing circuit definition for OpenFPGA architecture
|
2020-01-19 14:44:27 -07:00 |
|
tangxifan
|
ebe46d15a9
|
add XML parser, writer and linker for configuration protocol data structure
|
2020-01-18 21:19:20 -07:00 |
|
tangxifan
|
9693c3a12d
|
add XML writer for simulation setting object
|
2020-01-18 16:41:42 -07:00 |
|
tangxifan
|
bc3130d196
|
add XML parser for simulation setting
|
2020-01-18 15:40:20 -07:00 |
|
tangxifan
|
2a902c7e55
|
add mutators to simulation setting data structure
|
2020-01-18 14:07:37 -07:00 |
|
tangxifan
|
0de9908d52
|
add accessors to simulation setting data structure
|
2020-01-18 12:51:25 -07:00 |
|
tangxifan
|
7a46c85cb0
|
reorganize and clean-up sample architecture
|
2020-01-18 10:50:15 -07:00 |
|
tangxifan
|
ab1b1b7e02
|
add XML writer for technology library
|
2020-01-17 20:02:56 -07:00 |
|
tangxifan
|
8f2936af54
|
finish XML parser for technology library
|
2020-01-17 17:43:55 -07:00 |