tangxifan
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aef94171c2
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[doc] update options for pcf2place command
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2022-10-17 13:55:18 -07:00 |
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tangxifan
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58487c7766
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[doc] add more notes about the commmand ``pb_pin_fixup``
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2022-09-29 11:01:07 -07:00 |
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tangxifan
|
9b65472ffb
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[doc] update compilation guidelines
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2022-09-26 16:22:40 -07:00 |
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tangxifan
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48f776d49b
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[doc] update documentation about the new option
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2022-09-12 16:58:32 -07:00 |
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tangxifan
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0609210b39
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[doc] update doc with the new xml syntax
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2022-09-08 17:00:16 -07:00 |
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tangxifan
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50813d90a2
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[doc] update documentation based on the actual implementation on rr_gsb writer
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2022-08-29 20:45:31 -07:00 |
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tangxifan
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12a30196e0
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[engine] updating gsb writer; Unfinished!!!
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2022-08-29 16:58:48 -07:00 |
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tangxifan
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adbc69f081
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[doc] add new options for GSB writer
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2022-08-29 14:16:51 -07:00 |
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tangxifan
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77abb86dab
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[doc] update documentation about the activity file options
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2022-08-01 21:37:22 -07:00 |
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tangxifan
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84dbcd61dd
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[doc] fixed a few typo and format errors
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2022-07-28 19:09:53 -07:00 |
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tangxifan
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c16bcd7f63
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[doc] add file formates required by pcf2place
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2022-07-28 16:35:13 -07:00 |
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tangxifan
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860591ff3f
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[doc] add pcf file format to documentation
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2022-07-28 16:15:44 -07:00 |
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tangxifan
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6e5fde56ce
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[doc] add pcf2place to command list
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2022-07-28 16:06:57 -07:00 |
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tangxifan
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2b4beb632c
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[doc] fix a bug in including io information file format
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2022-07-26 15:50:35 -07:00 |
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tangxifan
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bf2b1da801
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[doc] add the new command file format to documentation
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2022-07-26 14:06:07 -07:00 |
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tangxifan
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21a0415ff3
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Update compile.rst
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2022-07-21 17:52:21 -07:00 |
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tangxifan
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929c74b3b0
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Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into hotfix_reg
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2022-05-23 09:11:18 +08:00 |
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tangxifan
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7a0f796b7c
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[doc] add missing file link and show version number in frontpage README
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2022-05-22 15:27:22 +08:00 |
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tangxifan
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78313b3593
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[Misc] Now version number is in a separated file; Cmakefile and doc read the file and build version number on fly; CI can also update version
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2022-05-22 15:22:43 +08:00 |
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tangxifan
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1794578b49
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[doc] code format
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2022-05-22 14:04:12 +08:00 |
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tangxifan
|
07df4611e8
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[doc] more tips
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2022-05-22 13:46:13 +08:00 |
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tangxifan
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61a1462c21
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[doc] add guidelines about running regression tests
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2022-05-22 13:44:48 +08:00 |
Ganesh Gore
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daae02a614
|
Minor documentation update
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2022-05-08 13:03:16 -06:00 |
|
Ganesh Gore
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1e243650b9
|
Added option to copy example projects
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2022-05-03 14:06:16 -06:00 |
|
Ganesh Gore
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42567d8178
|
Updated docuementation
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2022-05-02 12:56:31 -06:00 |
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tangxifan
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907308ee0f
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[Doc] Update bitstream distribution file format
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2022-03-29 20:09:24 +08:00 |
taoli4rs
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781250f0bb
|
Fix a small typo to trigger the CI flow.
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2022-03-22 16:36:45 -07:00 |
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tangxifan
|
6ff69d26b9
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[Doc] An example to the documentation about the new feature in tile_annotation
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2022-03-20 13:12:13 +08:00 |
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tangxifan
|
123bb70cb3
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[Doc] More explanantion on the use of config_enable attribute for circuit ports
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2022-02-23 15:53:58 -08:00 |
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tangxifan
|
b78e58d9bf
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[Doc] Update doc about big endian syntax in bus group file format
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2022-02-18 23:07:18 -08:00 |
|
tangxifan
|
8116141210
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[Doc] Update documentation on the bus group feature
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2022-02-18 15:46:25 -08:00 |
|
tangxifan
|
37d8617a5c
|
[Doc] Update due to new options
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2022-02-17 19:45:37 -08:00 |
|
tangxifan
|
4a78bcf5d3
|
[Doc] update file format about bus group
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2022-02-17 15:15:05 -08:00 |
|
tangxifan
|
f5e0d685cf
|
[Doc] Adjust figure width
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2022-02-17 14:29:09 -08:00 |
|
tangxifan
|
796428d848
|
[Doc] Add documentation about bus group file format
|
2022-02-17 14:22:21 -08:00 |
|
tangxifan
|
2b5fded2a9
|
[Doc] Update documentation on the new option
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2022-02-01 13:25:58 -08:00 |
|
tangxifan
|
b7b0a2a5d8
|
[Doc] Update doc about the new option
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2022-02-01 12:19:26 -08:00 |
|
tangxifan
|
63f44adf15
|
[FPGA-Verilog] Now have a new option ``--use_relative_path``
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2022-01-31 12:48:05 -08:00 |
|
tangxifan
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a9a56686e2
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[Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml``
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2022-01-26 11:10:29 -08:00 |
|
tangxifan
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25143d07f1
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[FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files
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2022-01-25 13:37:54 -08:00 |
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tangxifan
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a4659020f2
|
Merge branch 'master' into time_stamp
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2022-01-25 12:11:35 -08:00 |
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tangxifan
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62b57b05d2
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[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
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2022-01-25 12:09:08 -08:00 |
Aram Kostanyan
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758453f725
|
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
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bd158311c5
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Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
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2022-01-18 14:07:41 +05:00 |
|
Aram Kostanyan
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588ee14920
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Merge branch 'master' into issue-483
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2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
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fb2e4377c8
|
Added missing changes from previous commit.
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2022-01-17 19:42:40 +05:00 |
|
Aram Kostanyan
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2b008177e7
|
Updated documentation.
|
2022-01-17 14:58:20 +05:00 |
Awais Abbas
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54d4f30592
|
OpenFPGA Documentation updated for yosys only support
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2022-01-14 16:14:48 +05:00 |
|
tangxifan
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80c6d5887d
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Merge branch 'ql_mem_bank_opensource' of https://github.com/RapidSilicon/OpenFPGA_RS into ql_mem_bank
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2021-12-29 10:57:46 -08:00 |
|
tangxifan
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b2ba0d0c42
|
[Doc] Add version naming convention to developer guidelines
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2021-12-22 15:12:14 -08:00 |