tangxifan
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812af4f722
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[arch] add arch that supports negative edge triggered flip-flop
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2022-05-09 16:32:01 +08:00 |
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tangxifan
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d4992fd9ad
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[HDL] Add a multi-mode ff which can support posedge and negedge
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2022-05-09 15:52:17 +08:00 |
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tangxifan
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b27a04eb24
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[Test] Now test case has a config done CCFF
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2022-02-23 22:07:11 -08:00 |
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tangxifan
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ff264c00a2
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
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2021-10-31 11:51:34 -07:00 |
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tangxifan
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0a449cc24c
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[HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected
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2021-10-30 11:45:01 -07:00 |
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tangxifan
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0b06820177
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[HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals
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2021-10-01 17:06:35 -07:00 |
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tangxifan
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2ce2fb269a
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[HDL] Added a different FF model which is designed to drive WLW only
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2021-09-28 12:35:13 -07:00 |
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tangxifan
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6469ee3048
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[HDL] Update DFF modules by adding custom cells required by shift registers in BL/WLs
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2021-09-28 12:21:54 -07:00 |
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tangxifan
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477e535344
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[HDL] Added a multi-mode FF design with configurable asynchronous reset
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2021-07-02 11:13:03 -06:00 |
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tangxifan
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75a12e55de
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[HDL] Remove the instrusive signal initialization in the configuration flip-flop HDL codes
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2021-06-29 11:40:22 -06:00 |
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tangxifan
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adfea88be2
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[HDL] Rename multi-mode DFF module
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2021-04-21 20:06:03 -06:00 |
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tangxifan
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62497549b6
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[HDL] Add multi-mode DFF module
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2021-04-21 20:04:40 -06:00 |
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tangxifan
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709ee1b842
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[HDL] Update dff netlist for SCFF used in configuration chain
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2021-01-04 17:17:35 -07:00 |
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tangxifan
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722a9bcf63
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[HDL] Add scan-chain DFF cell with configuration enable signal
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2021-01-04 14:31:26 -07:00 |
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tangxifan
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ff53d2c375
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[HDL] Add new Scan-chain DFF cell
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2020-11-30 17:54:10 -07:00 |
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tangxifan
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1a79a55646
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[HDL] Add DFF cell with reset but only 1 output
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2020-11-06 11:19:19 -07:00 |
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tangxifan
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7d46b35296
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[HDL] Add single-output DFF HDL
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2020-11-06 10:18:37 -07:00 |
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tangxifan
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019208ec0f
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |