tangxifan
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272d1fffb7
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[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks
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2021-04-24 13:30:46 -06:00 |
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tangxifan
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5a519390ff
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[HDL] Enriched DFF model in yosys technology library
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2021-04-21 22:49:05 -06:00 |
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tangxifan
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8cbea6a268
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[HDL] Add technology library for customizable DFF synthesis
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2021-04-21 19:50:51 -06:00 |
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tangxifan
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0a15f366cb
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[HDL] Patch dff models used in yosys tech map
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2021-04-16 20:48:15 -06:00 |
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tangxifan
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ff4460695b
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[HDL] Add dff tech map files for yosys
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2021-04-16 17:00:55 -06:00 |
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tangxifan
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44d97ead86
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Merge branch 'master' into hetergeneous_arch
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2021-03-23 17:05:03 -06:00 |
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tangxifan
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b00b4f0f5f
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[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian
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2021-03-23 15:44:53 -06:00 |
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tangxifan
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a4bbffd1aa
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[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA
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2021-03-23 15:30:41 -06:00 |
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tangxifan
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477a522885
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[HDL] Rename tech lib to be consistent with arch name changes
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2021-03-20 18:08:03 -06:00 |
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tangxifan
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76113a80fa
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[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture
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2021-03-17 15:09:12 -06:00 |
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tangxifan
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cea43c2c45
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[HDL] Add SPRAM module to generic yosys tech lib for openfpga usage
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2021-03-16 18:04:31 -06:00 |
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tangxifan
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76837e02e6
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[Script] Rename yosys script supporting bram and restructure techlib files
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2021-03-16 16:16:53 -06:00 |