tangxifan
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8cc72536d1
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minor bug fixing
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2019-11-22 15:54:14 -07:00 |
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tangxifan
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a308a13d7c
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use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
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2019-11-05 15:41:59 -07:00 |
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tangxifan
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ebab0e91ef
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refactored include netlist writer
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2019-11-04 20:55:30 -07:00 |
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tangxifan
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358e9892ac
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reduce some error message to warnings
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2019-11-02 00:09:13 -06:00 |
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tangxifan
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7c116aac2f
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added Verilog generation for preconfig top module
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2019-10-29 13:54:35 -06:00 |
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tangxifan
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838173f3c4
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start refactoring bitstream generator
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2019-10-24 21:01:11 -06:00 |
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tangxifan
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cab4bd6807
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add gpio ports to pb_type modules
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2019-10-13 16:23:22 -06:00 |
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tangxifan
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663b1b7665
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refactorint net addition for configuration signals in module graph
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2019-10-11 13:07:14 -06:00 |
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tangxifan
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f2b3341d87
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developing verilog writer for generic module graph
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2019-10-10 20:09:55 -06:00 |
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tangxifan
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6bed89c237
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refactored counting config bits for circuit model and update Verilog generation for primitive pb_types
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2019-10-08 18:00:04 -06:00 |
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tangxifan
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433fc73460
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refactored local encoder support for Verilog MUX generation
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2019-09-27 23:10:43 -06:00 |
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tangxifan
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f0949fea2f
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Merge branch 'dev' into refactoring
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2019-09-27 18:09:58 -06:00 |
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tangxifan
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1e187f3d15
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start adding memory circuit to Switch blocks
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2019-09-27 18:08:37 -06:00 |
AurelienUoU
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640922accd
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-27 16:54:13 -06:00 |
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AurelienUoU
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a93d7e57f7
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Scan chain support in directlist
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2019-09-27 16:53:00 -06:00 |
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tangxifan
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dbe1625267
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Refactored Verilog wiring for formal verification ports in Switch Blocks
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2019-09-27 13:51:22 -06:00 |
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tangxifan
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ead014e7d8
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refactoring the configuration bus Verilog generation for MUXes
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2019-09-27 11:47:34 -06:00 |
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AurelienUoU
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056219f180
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Rename SCFF to CCFF, configuration chain flip flop
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2019-09-26 11:32:57 -06:00 |
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tangxifan
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009c0d63b5
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refactored the memory bank. Ready to plug-in the test
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2019-09-13 15:05:31 -06:00 |
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tangxifan
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99c30fa7dd
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keep refactoring the memory Verilog generation
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2019-09-13 14:02:04 -06:00 |
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tangxifan
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79fa858f36
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remove unused ports for Verilog modules
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2019-09-11 19:39:59 -06:00 |
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tangxifan
|
0399319212
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refactored LUT Verilog generation
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2019-09-11 17:04:43 -06:00 |
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tangxifan
|
62853c092f
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refactoring local encoders. Ready to plug in
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2019-09-10 15:16:29 -06:00 |
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tangxifan
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59edd49862
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refactored CMOS MUX buffering
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2019-09-06 16:39:34 -06:00 |
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tangxifan
|
bc9d95408e
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bug fixed and refactored intermediate buffer addition
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2019-09-05 16:09:28 -06:00 |
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tangxifan
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e623c19055
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implementing mux Verilog generation. Bugs detected, fixing ongoing
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2019-09-04 23:54:53 -06:00 |
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tangxifan
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fde9c8b4ec
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add frac_lut outputs to mux_graph generation
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2019-09-03 23:19:24 -06:00 |
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tangxifan
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4d183a3fe4
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start developing mux Verilog module generation
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2019-09-03 16:59:03 -06:00 |
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tangxifan
|
39853408dd
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add recursive global port searching for circuit library
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2019-08-23 20:23:41 -06:00 |
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tangxifan
|
732e24767f
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developing module manager
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2019-08-22 23:49:35 -06:00 |
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tangxifan
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5a40c6713d
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managed to plug in refactored essential gates, dead codes to be removed
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2019-08-21 21:50:26 -06:00 |
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tangxifan
|
b08ff465c9
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refactored pass-gate verilog generation
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2019-08-21 17:33:16 -06:00 |
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tangxifan
|
9c43b1b753
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complete refacotriing the inv and buf part in submodules
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2019-08-21 14:54:05 -06:00 |
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tangxifan
|
a40e5c91ca
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refactored power-gate inverter
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2019-08-20 21:56:55 -06:00 |
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tangxifan
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5f55fc7b49
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add missing files and developing essential gates
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2019-08-20 20:43:46 -06:00 |
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tangxifan
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29104b6fa5
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rework on the circuit model ports and start prototyping mux Verilog generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
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a7ac1e4980
|
remame methods in circuit_library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
dcca9f4f0f
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finish mux graph builders
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2019-08-20 15:24:52 -06:00 |
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tangxifan
|
638969c3c9
|
adding mux graph data structures
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2019-08-20 15:24:52 -06:00 |
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tangxifan
|
c7526cb43c
|
memory sanitized
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2019-08-13 14:19:40 -06:00 |
|
tangxifan
|
ef4d15df4e
|
reorganize the libarchfpga repository
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2019-08-13 13:37:35 -06:00 |
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tangxifan
|
392f579836
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add linking functions for circuit models and architecture, memory sanitizing is ongoing
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2019-08-13 13:25:23 -06:00 |
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tangxifan
|
c56f289d3e
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add checkers for circuit library
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2019-08-12 16:45:33 -06:00 |
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tangxifan
|
d4ae160d3a
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start adding circuit library checkers
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2019-08-12 14:20:11 -06:00 |
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tangxifan
|
fbdab32a2d
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timing graph for circuit models are working
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2019-08-10 13:03:24 -06:00 |
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tangxifan
|
c004699a14
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complete parsers for ports
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2019-08-09 21:00:41 -06:00 |
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tangxifan
|
2c7d6e3de4
|
adding port parsers
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2019-08-09 17:48:55 -06:00 |
|
tangxifan
|
f80e58c753
|
developing a in-house tokenizer
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2019-08-09 16:36:22 -06:00 |
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tangxifan
|
3d7adb3dd9
|
start developing parsers for delay values
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2019-08-09 15:52:28 -06:00 |
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tangxifan
|
6b5ac2e1ef
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add timing graph builder for circuit models
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2019-08-09 12:45:03 -06:00 |