tangxifan
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1fd399736d
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[Tool] Patch FPGA-SDC to consider time unit in global port timing constraints
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2021-05-27 10:26:20 -06:00 |
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tangxifan
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c8d41b4e69
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[Tool] Change routing module port naming to include architecture port names
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2021-03-14 19:35:49 -06:00 |
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tangxifan
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6a0f4f354f
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[Tool] Support superLUT circuit model in core engine
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2021-02-09 20:23:05 -07:00 |
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tangxifan
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87b2c1f3b8
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[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
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2021-01-15 12:01:53 -07:00 |
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tangxifan
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5be9e9b736
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[Tool] Adapted tools to support I/O in center grid
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2020-12-04 18:50:13 -07:00 |
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tangxifan
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81e56d45d6
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[Tool] Update FPGA-SDC to use the new data structure for global ports
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2020-11-10 21:17:17 -07:00 |
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tangxifan
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c61ec5a8b8
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[Tool] Bug fix for defining global ports from tiles
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2020-11-10 20:31:14 -07:00 |
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tangxifan
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4a2874b2bc
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[Tool] Refactor the codes for walking through io blocks
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2020-11-03 13:21:50 -07:00 |
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tangxifan
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e4d974c5c8
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[Tool] Split io location mapping builder from fabric builder
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2020-11-02 18:27:34 -07:00 |
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tangxifan
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721bcce373
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[Tool] Change analysis SDC file name to track netlist name
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2020-10-10 17:43:35 -06:00 |
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tangxifan
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1b55dfb441
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hotfix on treating the dangling ports in pb_graph for analysis SDC generator
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2020-07-09 23:28:42 -06:00 |
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tangxifan
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0a3c746fb1
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now split CB module bus ports into lower/upper parts
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2020-07-01 14:37:13 -06:00 |
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tangxifan
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05187f8aa4
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use typedef to short the module pin information
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2020-06-30 18:07:22 -06:00 |
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tangxifan
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2e7684b746
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adapt bus ports in connection block module builder
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2020-06-30 17:50:53 -06:00 |
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tangxifan
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2ef083c49d
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adapt SB module builder to use bus ports
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2020-06-30 16:02:40 -06:00 |
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tangxifan
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e089b0ef22
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use constant string for inverted port naming
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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8915d10d27
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add verbose output option to configure port disable timing writer
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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6177921d4c
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bug fixed in configure port disable timing. Now we disable the right ports of LUTs
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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067d09f954
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bug fix for configure port disable_timing writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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13f591cacf
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add new command to disable timing for configure ports of programmable modules
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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ae9f1fbd90
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critical bug fixed in the disable MUX output
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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99751b84f5
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bug fix in configuration chain sdc writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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02e86c565a
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bug fix in configuration chain SDC writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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4c0953415b
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add configuration chain sdc writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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dad99d13a2
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bug fixed in SDC timing writer for primitive pb_type
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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b8a79c563d
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bug fix in the SDC port generation
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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84d24ad075
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bug fix in pnr sdc grid writer for module paths in hierarchical view
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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99fa51cb49
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bug fixed in the SDC CB hierarchy writer
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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10e1a4b2fe
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format fix in the fabric hierarchy and grid SDC hierarchy to be complaint to YAML format
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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cc6d988872
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bug fix in grid SDC generator
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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b167c85980
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fully expand grid hierarchy in SDC writer
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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55518f4cec
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minor fix in the sdc hierarchy writer for grids
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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b57a90a6ca
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add SDC hierarchy writer for grids and now support flatten hierarchy in grid timing constraints
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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d9dc7160a7
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minor fix on the hierarchy writer in SDC generator
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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17c254a370
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add missing file to follow up the previous commit
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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c651df6421
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add hierarchy writer to SDC generator
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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0985c720e9
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remove regexp in SDC generation.
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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8726c618eb
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add time unit support on SDC generator. Now users can define time_unit thru cmd-line options
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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0e44cf3ea3
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now SDC to disable routing multiplexer outputs can use wildcards
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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609115e51f
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now hierarchical SDC generation is applicable to CB timing constraints
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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7e82c23f52
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now add SDC generator supports both hierarchical and flatten in writing timing constraints
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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7503c58fb2
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small fix on SDC generator for SB which do not exist in FPGA
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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d0793d9029
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now disable_sb_output support wildcard
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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8695c5ee78
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add options to use general-purpose wildcards in SDC generator
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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facd87dafe
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use wildcard in SDC generation for multiple-instanced-blocks
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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2e3054f79a
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bug fixed for SDC generation for LUTs
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2020-04-21 14:34:51 -06:00 |
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tangxifan
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68b7991a46
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bug fixed for sdc on memory blocks
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2020-04-21 13:37:56 -06:00 |
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tangxifan
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3f1fb70d16
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FPGA SDC now constrain max and min delay for primitive modules in grids
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2020-04-21 11:00:28 -06:00 |
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tangxifan
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c2804a4c1f
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bug fix for RC delay computing in SDC generation
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2020-04-20 22:20:00 -06:00 |
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tangxifan
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1a8968cb37
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now FPGA-SDC will constrain timing for routing tracks using the VPR Rmetal parameter in ARCH XML
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2020-04-20 21:12:51 -06:00 |