Ganesh Gore
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0cc439f76c
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Working lattice benchmark unclean commit
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2019-08-08 18:08:39 -06:00 |
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Ganesh Gore
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54f6ca2687
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Added lattice benchmark settings
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2019-07-01 11:07:23 -06:00 |
AurelienUoU
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a2f6ded2a2
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Add path modification in file changing a keyword into OpenFPGA full path
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2019-06-04 15:21:15 -06:00 |
tangxifan
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ec3b4c86c4
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update file organization and be ready for SB/CB class
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2019-05-21 12:15:38 -06:00 |
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AurelienUoU
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fbebb45bf2
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Path correction in config file
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2019-05-20 11:13:30 -06:00 |
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AurelienUoU
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df8bb0db1a
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Add MCNC Benchmarks netlists generation to travis regression test
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2019-05-17 15:22:04 -06:00 |
Baudouin Chauviere
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79930982cf
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Changed for the naming
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2018-12-08 16:19:38 -07:00 |
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tangxifan
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b3c1018e28
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fixed a bug in wired LUT
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2018-12-06 16:50:30 -07:00 |
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tangxifan
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4f5f8de46f
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Add Yosys and update flow_flow Perl Script
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2018-11-30 21:14:43 -07:00 |
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Baudouin Chauviere
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d55ecd154b
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Add the PTM to the benchmark flow
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2018-11-21 11:32:34 -07:00 |
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Baudouin Chauviere
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8ce0a84bc1
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Correction of the global make, the fpga_flow and the doc
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2018-11-20 14:47:15 -07:00 |
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Baudouin Chauviere
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03e902023a
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Perl script integrated to flow. rm shell one
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2018-11-20 13:32:11 -07:00 |
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Baudouin Chauviere
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15d69e2bb1
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Generation script finished TODO: integration in flow
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2018-11-20 13:24:31 -07:00 |
Baudouin Chauviere
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9611576d6a
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Update on the examples to respect the new syntax
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2018-11-19 15:50:29 -07:00 |
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Baudouin Chauviere
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e5c6471fc2
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Update of the Readme and added an example
ReadMe is now cleaner
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2018-10-03 17:10:29 -06:00 |
Xifan Tang
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1cf066d3ad
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Fixing minor bugs
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2018-09-06 14:25:23 -06:00 |
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Xifan Tang
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c009a37580
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fix minor bugs
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2018-09-04 17:56:37 -06:00 |
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Xifan Tang
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00ecd0bb1d
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Cleanup codes and organization
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2018-09-04 17:31:30 -06:00 |
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Xifan Tang
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90669d19c5
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Update FPGA-SPICE and flow configurations
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2018-08-09 11:27:16 -06:00 |
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Xifan Tang
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158dec405e
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Reorganize the code directory
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2018-07-26 11:28:21 -06:00 |