tangxifan
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3647548526
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clean up on the shell echo commands
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2020-03-20 11:07:45 -06:00 |
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tangxifan
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808853db0b
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critical bug fixed for find proper pb_route traceback
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2020-03-13 12:26:37 -06:00 |
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tangxifan
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81e5af464e
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improve lb_route to avoid routing combinational loops
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2020-03-12 23:58:56 -06:00 |
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tangxifan
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773e6da308
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Spot a bug in lb router where path finder fail to use low-occupancy node when expanding the tree
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2020-03-12 22:53:17 -06:00 |
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tangxifan
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f90dc5c296
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remove redundant XML codes
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2020-03-12 20:44:07 -06:00 |
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tangxifan
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29450f3472
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debugging multi-source lb router
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2020-03-12 20:42:41 -06:00 |
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tangxifan
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8921905bec
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annotate multiple-source and multiple-sink nets from pb to lb router
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2020-03-12 19:21:13 -06:00 |
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tangxifan
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f0b22aaa11
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Make lb router support multiple sources to be routed
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2020-03-12 13:44:14 -06:00 |
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tangxifan
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c40675ca9d
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minor code formatting
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2020-03-12 11:55:25 -06:00 |
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tangxifan
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f1e8e78410
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minor code formatting
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2020-03-12 11:47:42 -06:00 |
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tangxifan
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689c50dff1
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label the routing status for each sink in lb_router
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2020-03-12 11:36:31 -06:00 |
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tangxifan
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a1f19e776e
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Add comments to lb router and extract a private function for routing a single net
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2020-03-12 11:05:38 -06:00 |
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tangxifan
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cd50155e29
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rename variables in lb router
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2020-03-12 10:24:38 -06:00 |
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tangxifan
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17a1c61b9d
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minor change in variable names in lb_router
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2020-03-11 21:10:16 -06:00 |
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tangxifan
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8e796f152f
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add comments to lb_router about how-to-use
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2020-03-11 21:05:06 -06:00 |
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tangxifan
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2a260a05aa
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add a microbenchmark `and_latch` to test LUTs in wired mode
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2020-03-11 10:40:59 -06:00 |
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tangxifan
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1d766d2a70
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minor format fix on documentation
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2020-03-11 10:22:30 -06:00 |
|
Xifan Tang
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b941ac8a4a
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remove deprecated options
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2020-03-10 20:58:00 -06:00 |
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Xifan Tang
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8037d1ad93
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-03-10 20:55:02 -06:00 |
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Xifan Tang
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9f743f7f4e
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add openfpga shell documentation
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2020-03-10 20:54:42 -06:00 |
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tangxifan
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0da6f00af5
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start reworking the openfpga tool documentation
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2020-03-10 17:29:35 -06:00 |
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tangxifan
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089cc5e86e
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update documentation on circuit model annotation on VPR architecture
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2020-03-10 16:51:50 -06:00 |
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tangxifan
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7195564455
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reworked circuit model examples in documentation. Now we are consistent to latest syntax
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2020-03-10 16:17:20 -06:00 |
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tangxifan
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8db257946c
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remove backport in travis setup. The link is dead now. Plus we no longer need the backport for a newer version of cmake
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2020-03-10 12:18:39 -06:00 |
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tangxifan
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54dfdc0cc1
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update general documentation on circuit library
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2020-03-10 12:18:12 -06:00 |
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tangxifan
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2a3c5b98a5
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minor format fix in documentation
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2020-03-09 21:25:13 -06:00 |
|
Xifan Tang
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d14fa16905
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finish documentation update on technology library
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2020-03-09 21:17:25 -06:00 |
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Xifan Tang
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cb7e4a1dfa
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finish documentation the simulation settings in VPR8 integration
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2020-03-09 20:03:37 -06:00 |
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tangxifan
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751735bf41
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update documentation in simulation setting syntax
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2020-03-09 17:40:33 -06:00 |
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tangxifan
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3c7fd30e12
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merged tutorial to online documentation and reworked compilation guidelines
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2020-03-09 13:58:24 -06:00 |
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tangxifan
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af6319a6b0
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reworked motivation in documentation
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2020-03-09 11:27:25 -06:00 |
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tangxifan
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73da4a1d6e
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rework motivation for FPGA-Verilog and FPGA-Bitstream in documentation
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2020-03-09 10:32:03 -06:00 |
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tangxifan
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f821e60405
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clean up deadlinks in doc
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2020-03-09 10:15:16 -06:00 |
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tangxifan
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1f092171f2
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Merge branch 'refactoring' into dev
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2020-03-09 09:45:31 -06:00 |
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tangxifan
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d61ae5561b
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start cleanup the documentation for openfpga shell
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2020-03-09 09:44:19 -06:00 |
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tangxifan
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94d9b6e615
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Merge branch 'refactoring' into dev
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2020-03-09 09:35:59 -06:00 |
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tangxifan
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3aca7b498c
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Show help desk when a command is called inside shell without satisfying the dependency
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2020-03-09 09:34:21 -06:00 |
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tangxifan
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2f38b5cbc2
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Merge branch 'refactoring' into dev
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2020-03-08 16:23:20 -06:00 |
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tangxifan
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aff73bdd74
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deployed edge sorting and make it as an option to link_arch command
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2020-03-08 15:59:53 -06:00 |
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tangxifan
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b80e26e711
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update bitstream generator to use sorted edges
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2020-03-08 15:36:47 -06:00 |
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tangxifan
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5558932762
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use sorted edges in building routing modules
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2020-03-08 15:31:41 -06:00 |
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tangxifan
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7a7f8374b3
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start deploying edge sorting in uniquifying SB modules
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2020-03-08 15:24:34 -06:00 |
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tangxifan
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f9499afe04
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remove unused variable
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2020-03-08 15:00:01 -06:00 |
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tangxifan
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0c7aa2581d
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update vpr8 version with hotfix on undriven pins in GSB
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2020-03-08 14:58:56 -06:00 |
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tangxifan
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b219b096ee
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hotfix on removing dangling inputs from GSB, which are CLB direct output
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2020-03-08 13:54:49 -06:00 |
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tangxifan
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b2534f1a09
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Merge branch 'refactoring' into dev
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2020-03-07 23:31:45 -07:00 |
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tangxifan
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0fbf3fca41
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start developing edge sorting inside RRGSB
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2020-03-07 23:30:55 -07:00 |
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tangxifan
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8b40ca2990
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Merge branch 'refactoring' into dev
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2020-03-07 17:54:13 -07:00 |
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tangxifan
|
ca92c2717f
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bug fix for tile directs
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2020-03-07 16:00:32 -07:00 |
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tangxifan
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e48c2b116d
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bug fixing for duplicated grid pin names
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2020-03-07 15:46:12 -07:00 |