Commit Graph

18 Commits

Author SHA1 Message Date
tangxifan 63f44adf15 [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
tangxifan 62b57b05d2 [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
tangxifan c84c0d4a3f [FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR 2021-09-20 17:07:26 -07:00
tangxifan 15e26a5602 [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
tangxifan b78f8bec16 [Tool] Bug fixed for multi-region configuration frame 2020-10-30 21:19:20 -06:00
tangxifan 3c10af7f2b bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm 2020-06-11 19:31:14 -06:00
tangxifan 8267dad8ef add decoder support for Z signals 2020-06-11 19:31:14 -06:00
tangxifan c85ccceac7 try bug fixing in memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan 0bee70bee6 finish memory bank configuration protocol support. 2020-06-11 19:31:13 -06:00
tangxifan 31c9a011dd keep bug fixing for arch decoders 2020-06-11 19:31:11 -06:00
tangxifan 986956e474 bug fix for arch decoder Verilog codes. Now Modelsim compiles ok. 2020-06-11 19:31:11 -06:00
tangxifan 6a72c66eb8 bug fixed for frame-based configuration memory in top-level full testbench 2020-06-11 19:31:11 -06:00
tangxifan 8aa665b3b2 bug fix in the Verilog codes for frame decoders 2020-06-11 19:31:10 -06:00
tangxifan 5c5a044c68 add architecture decoder (for frame-based config memory) to Verilog writer 2020-06-11 19:31:09 -06:00
tangxifan 8f5a684b10 removed redundant include files in all the verilog netlists except the top one 2020-06-11 19:28:13 -06:00
tangxifan e811f8bb21 plug in netlist manager and now the include_netlist appears in one unique file 2020-04-23 20:42:11 -06:00
tangxifan 60f40a9657 use constant module manager as much as possible in Verilog writer 2020-02-16 16:35:26 -07:00
tangxifan a88c4bc954 add decode utils to libopenfpga and adapt local decoder writer in Verilog 2020-02-16 12:21:59 -07:00