tangxifan
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4aa6264b1c
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[Tool] Rework simulation time period to be sync with actual stimuli
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2020-12-02 22:58:13 -07:00 |
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tangxifan
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c82f01b3ab
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[Tool] Use conditional operator in signal initialization to eliminate all the warning messages
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2020-11-23 15:50:23 -07:00 |
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tangxifan
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e644545f21
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[Doc] Remove signal initialization for select ports of MUXes and Pass-gates; Use urandom to generate just-fit random vectors
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2020-11-23 15:02:06 -07:00 |
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tangxifan
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3b2a4c5387
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[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
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2020-11-22 20:25:03 -07:00 |
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tangxifan
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37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
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tangxifan
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e4d974c5c8
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[Tool] Split io location mapping builder from fabric builder
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2020-11-02 18:27:34 -07:00 |
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tangxifan
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bba476fef4
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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1e2226e1c3
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now use explicit port mapping in the verilog testbenches for reference benchmarks
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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ff9cc50527
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relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
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2020-03-27 20:09:50 -06:00 |
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tangxifan
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80bb2baae5
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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tangxifan
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ae899f3b11
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bug fixed for clock names
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2020-02-27 16:51:55 -07:00 |
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tangxifan
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9b769cd8e4
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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tangxifan
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25e0583636
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |