tangxifan
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c63cee458b
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[script] adapt code format for python
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2024-04-10 12:58:05 -07:00 |
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tangxifan
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2bd60dad11
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[script] now timing extraction focus on the last found results
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2023-12-12 14:10:13 -08:00 |
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tangxifan
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592e2e310c
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[script] typo
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2023-12-12 13:45:23 -08:00 |
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tangxifan
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f689ef7654
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[script] format
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2023-12-12 13:15:03 -08:00 |
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tangxifan
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4c0f6e2273
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[script] syntax
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2023-12-12 13:14:47 -08:00 |
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tangxifan
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e753e6d22c
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[script] syntax
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2023-12-12 13:13:51 -08:00 |
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tangxifan
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d9db78ac30
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[script] now run fpga task has a new option ``default_tool_path``
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2023-12-12 13:11:48 -08:00 |
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tangxifan
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1a4aaaf759
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[script] update openfpga flow to support args for default tool path
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2023-12-12 10:00:50 -08:00 |
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tangxifan
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dba48fb171
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[test] reworking adder mapping flow to validate carry chain mapping
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2023-06-20 16:57:08 -07:00 |
Ganesh Gore
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a6263c44af
|
Updated format
|
2023-02-11 18:12:04 -07:00 |
|
Ganesh Gore
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2afb91596f
|
Refactored run_openfpga_task.py
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2023-02-11 18:04:54 -07:00 |
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tangxifan
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97c72c73f1
|
[test] add a small test to validate tcl integration
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2022-12-02 11:43:46 -08:00 |
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tangxifan
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729a3a0249
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[engine] tcl integration has initial success. Upload example scripts
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2022-12-01 16:31:15 -08:00 |
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tangxifan
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9d8f4c1664
|
[script] format python codes
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2022-11-21 14:21:31 -08:00 |
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tangxifan
|
abee802830
|
[script] now build task_result.csv from openfpgashell.log rather than vpr_stdout.log because of missing block usage numbers
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2022-09-20 13:46:30 -07:00 |
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tangxifan
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373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-16 16:47:21 -07:00 |
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tangxifan
|
a8d7b6c2c4
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[script] add a python script for users to visualize the I/O sequence
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2022-09-16 10:49:10 -07:00 |
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tangxifan
|
6c44f321e5
|
[script] fixed a bug
|
2022-08-22 18:24:26 -07:00 |
|
tangxifan
|
2bbf2f02c9
|
[script] now return status on each arch upgrade task
|
2022-08-22 18:23:00 -07:00 |
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tangxifan
|
3c9c11d451
|
[script] working on formatting
|
2022-08-22 18:02:38 -07:00 |
|
tangxifan
|
55e765a206
|
[script] slight improve on formatting
|
2022-08-22 18:00:14 -07:00 |
|
tangxifan
|
4a7c3fce93
|
[script] debugging format
|
2022-08-22 17:04:30 -07:00 |
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tangxifan
|
2f5ea0cabb
|
[script] functional arch file converter; need to clean up formatting issues
|
2022-08-22 16:40:49 -07:00 |
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tangxifan
|
4efc506762
|
[script] now change to use minidom and debugging the child removal
|
2022-08-22 16:33:49 -07:00 |
|
tangxifan
|
880d7122bf
|
[script] complete code; start debugging on arch file converter
|
2022-08-22 12:29:49 -07:00 |
|
tangxifan
|
5134ea2233
|
[script] save progress
|
2022-08-22 11:00:46 -07:00 |
|
tangxifan
|
a61d6a2685
|
[script] developing arch converting script
|
2022-08-22 10:34:29 -07:00 |
|
tangxifan
|
9ea4a7c90f
|
[script] fixed a bug
|
2022-08-01 19:18:41 -07:00 |
|
tangxifan
|
55c7b75ab6
|
[script] even when power analysis mode is turned off, if users define a act file, still use it
|
2022-08-01 18:13:57 -07:00 |
root
|
0da44ad1fc
|
[script] now .act file is no longer required in openfpga_flow/task when power analysis option is off
|
2022-08-02 08:02:28 +08:00 |
|
Ganesh Gore
|
daae02a614
|
Minor documentation update
|
2022-05-08 13:03:16 -06:00 |
|
tangxifan
|
74045fc7a1
|
[Script] Fix a bug
|
2022-02-14 23:11:42 -08:00 |
|
tangxifan
|
2990eb7406
|
[Script] Fixed a bug in task run when removing previous runs
|
2022-02-14 22:54:16 -08:00 |
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tangxifan
|
1d3c9ff192
|
[Script] Adapt python scripts to support include directory
|
2022-02-01 13:55:25 -08:00 |
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tangxifan
|
dd40057992
|
[Script] Fixed a bug which causes errors when removing run-directory
|
2022-01-25 13:56:42 -08:00 |
Aram Kostanyan
|
758453f725
|
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
|
2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
|
588ee14920
|
Merge branch 'master' into issue-483
|
2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
|
fb2e4377c8
|
Added missing changes from previous commit.
|
2022-01-17 19:42:40 +05:00 |
|
Aram Kostanyan
|
6a4cc340a3
|
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
|
2022-01-17 13:21:29 +05:00 |
Awais Abbas
|
fc52a4696c
|
Yosys only support added in OpenFPGA
|
2022-01-06 14:44:11 +05:00 |
nadeemyaseen-rs
|
1ea56b2d18
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-11-18 00:00:55 +05:00 |
|
Aram Kostanyan
|
a355977420
|
Adding Yosys+Verific support.
|
2021-10-29 18:34:27 +05:00 |
|
nadeemyaseen-rs
|
274252438a
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-10-20 20:13:46 +05:00 |
Christophe Alexandre
|
c42acec81e
|
Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py
|
2021-10-18 10:45:35 +00:00 |
|
Christophe Alexandre
|
c3dd704bf3
|
Fixing typo in run_fpga_flow.py
|
2021-10-18 09:13:42 +00:00 |
|
Christophe Alexandre
|
d411967159
|
Fixing small typo in run_fpga_flow.py
|
2021-10-15 10:01:12 +00:00 |
|
tangxifan
|
6adf439081
|
Merge remote-tracking branch 'upstream/master'
|
2021-09-01 14:19:00 -07:00 |
Will
|
c31c1d8b04
|
Accept absolute project paths as inputs to the 'run_fpga_task.py' script.
|
2021-08-13 11:08:09 -04:00 |
|
tangxifan
|
8baf60603a
|
[Script] Patching the run_fpga_task.py on pin constraint files
|
2021-07-02 15:59:29 -06:00 |
|
Ganesh Gore
|
c67807868c
|
[bugFix] Benchamrk variable declaration
|
2021-07-02 15:26:39 -06:00 |