tangxifan
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3c0faf0021
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[OpenFPGA Architecture] Add a new architecture with fully connected crossbar at CLB outputs
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2020-09-16 17:27:24 -06:00 |
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tangxifan
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6c925dcded
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[regression test] Add more tests for thru channels and deploy to CI
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2020-08-19 20:11:37 -06:00 |
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tangxifan
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881672d46a
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update thru channel arch for avoid buggy pin locations
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2020-08-19 19:52:35 -06:00 |
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tangxifan
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3273f441fe
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bug fix in the flagship vpr arch
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2020-08-19 15:23:20 -06:00 |
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tangxifan
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d7efdf35b6
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add custom pin location to the flagship vpr arch with frac mem and dsp
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2020-08-19 11:15:25 -06:00 |
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tangxifan
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3ee4e10aa8
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bug fix in the frac mem & DSP vpr arch
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2020-08-18 17:25:45 -06:00 |
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tangxifan
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f833e0ec66
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add a flagship architecture using fracturable memory and dsp
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2020-08-17 17:49:51 -06:00 |
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tangxifan
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1ca2829868
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update readme for vpr architecture naming
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2020-08-17 13:54:26 -06:00 |
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tangxifan
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534c609e17
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add fixed layouts to a flagship architecture to test bitstream generation runtime
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2020-07-28 11:51:50 -06:00 |
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tangxifan
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f754c8af06
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use k6_n10 architecture to reduce CI runtime
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2020-07-22 13:45:55 -06:00 |
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tangxifan
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1e6955aaa4
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |