tangxifan
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d6fe414cd1
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Merge pull request #1485 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2023-12-10 19:45:28 -08:00 |
github-actions[bot]
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8def72ee01
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Updated Patch Count
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2023-12-10 00:02:47 +00:00 |
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tangxifan
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b494740781
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Merge pull request #1484 from lnis-uofu/xt_hotfix
Support VCS simulator for QL memory bank in full testbench
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2023-12-08 16:35:47 -08:00 |
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tangxifan
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2879bf2e6e
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[doc] add new option
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2023-12-08 13:56:46 -08:00 |
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tangxifan
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5c839c1858
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[test] debug
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2023-12-08 13:52:52 -08:00 |
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tangxifan
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6a5df804b9
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[test] add new testcase to reg test
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2023-12-08 13:46:54 -08:00 |
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tangxifan
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99f1c5493c
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[test] add a new testcase to support vcs
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2023-12-08 13:45:23 -08:00 |
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tangxifan
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bacd845139
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[core] code format
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2023-12-08 13:41:41 -08:00 |
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tangxifan
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5e181cbe72
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[core] add a new option for simulator type to verilog full testbench generator
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2023-12-08 13:07:25 -08:00 |
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tangxifan
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0e945d6e71
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[core] fix a bug in ql memory bank tb where VCS failed
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2023-12-08 11:36:54 -08:00 |
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tangxifan
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8fe9811326
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Merge pull request #1482 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2023-12-06 16:06:08 -08:00 |
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github-actions[bot]
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8f13674e80
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Updated Patch Count
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2023-12-07 00:02:28 +00:00 |
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tangxifan
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f6caa148e3
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Merge pull request #1481 from lnis-uofu/xt_ci
[ci] format labeler
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2023-12-06 12:41:18 -08:00 |
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tangxifan
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98c9290636
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[ci] format labeler
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2023-12-06 12:35:45 -08:00 |
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tangxifan
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60b3df0111
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Merge pull request #1476 from lnis-uofu/tangxifan-patch-2
Update labeler.yml to use v4 version. Since v5 introduces breaking ch…
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2023-12-06 11:15:13 -08:00 |
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tangxifan
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ebe17baf7c
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Merge branch 'tangxifan-patch-2' of github.com:lnis-uofu/OpenFPGA into tangxifan-patch-2
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2023-12-06 11:12:35 -08:00 |
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tangxifan
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7cc43dea4a
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[ci] debugging
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2023-12-06 11:11:55 -08:00 |
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tangxifan
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4fd71ed34a
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Merge branch 'master' into tangxifan-patch-2
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2023-12-05 21:39:58 -08:00 |
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tangxifan
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33f0f0feed
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[ci] typo
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2023-12-05 21:09:43 -08:00 |
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tangxifan
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77d55ae0b4
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Merge pull request #1457 from lnis-uofu/repack_debug
Repack debug
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2023-12-05 18:03:46 -08:00 |
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tangxifan
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7a41aaf19b
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[ci] typo
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2023-12-05 17:55:04 -08:00 |
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tangxifan
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95703fd9e6
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[ci] use checkout in labeler; following the latst documentation https://github.com/actions/labeler#using-configuration-path-input-together-with-the-actionscheckout-action
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2023-12-05 17:53:22 -08:00 |
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tangxifan
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e28b714305
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Merge branch 'master' into repack_debug
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2023-12-05 16:14:35 -08:00 |
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tangxifan
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1012059227
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Merge pull request #1475 from lnis-uofu/revert-1473-dependabot/submodules/yosys-2ffea67
Revert "Bump yosys from `8bd681a` to `2ffea67`"
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2023-12-05 16:13:12 -08:00 |
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tangxifan
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ce4f7d0719
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Update labeler.yml to use v4 version. Since v5 introduces breaking changes, which takes time to adapt
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2023-12-05 10:56:27 -08:00 |
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tangxifan
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0a1780b15a
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Revert "Bump yosys from `8bd681a` to `2ffea67`"
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2023-12-05 10:49:19 -08:00 |
Yitian4Debug
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d719dabe62
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Merge pull request #1474 from lnis-uofu/master
Sync up to master
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2023-12-05 10:29:55 -08:00 |
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Yitian4Debug
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8a24b1ba8c
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Update repack_option.h
code clean up
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2023-12-05 10:17:52 -08:00 |
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Yitian4Debug
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94f7b2f4e2
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Update repack.cpp
code clean up
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2023-12-05 10:16:10 -08:00 |
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Yitian4Debug
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1d0d8c5417
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Update read_xml_repack_design_constraints.cpp
code clean up
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2023-12-05 10:13:53 -08:00 |
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Yitian4Debug
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e6c9d22ce9
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Update repack_design_constraints.h
code clean up
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2023-12-05 10:10:19 -08:00 |
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Yitian4Debug
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aa51b6d388
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Update repack_design_constraints.h
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2023-12-05 09:40:25 -08:00 |
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Yitian4Debug
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57f3b7af0f
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Update repack_design_constraints.h
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2023-12-05 09:38:27 -08:00 |
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Yitian4Debug
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b765410300
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Update repack_design_constraints.cpp
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2023-12-05 09:37:56 -08:00 |
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Yitian4Debug
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d2379cfff6
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Update repack_option.h
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2023-12-05 09:34:34 -08:00 |
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Yitian4Debug
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231cb0f89b
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Update repack_option.cpp
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2023-12-05 09:30:32 -08:00 |
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Yitian4Debug
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83fdaea13d
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Update repack.cpp
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2023-12-05 09:28:27 -08:00 |
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tangxifan
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2568b9bc09
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Merge pull request #1473 from lnis-uofu/dependabot/submodules/yosys-2ffea67
Bump yosys from `8bd681a` to `2ffea67`
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2023-12-05 09:27:43 -08:00 |
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Yitian4Debug
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7aa882f82c
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Update read_xml_repack_design_constraints.cpp
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2023-12-05 09:26:05 -08:00 |
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Yitian4Debug
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0e243d1c05
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Update repack_design_constraints.cpp
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2023-12-05 09:17:29 -08:00 |
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Yitian4Debug
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d0958fc017
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Update repack_design_constraints.h
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2023-12-05 09:09:45 -08:00 |
dependabot[bot]
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c2db3706c8
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Bump yosys from `8bd681a` to `2ffea67`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `8bd681a` to `2ffea67`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](8bd681acfc...2ffea67b04)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
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2023-12-05 07:54:43 +00:00 |
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tangxifan
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fffc8ffb44
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Merge pull request #1472 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2023-12-04 17:49:35 -08:00 |
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github-actions[bot]
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df8a22191a
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Updated Patch Count
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2023-12-05 00:02:14 +00:00 |
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tangxifan
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c2b27293ac
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Merge pull request #1467 from lnis-uofu/treelin611-patch-1
Update repack_design_constraints.rst
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2023-12-04 14:10:37 -08:00 |
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Yitian4Debug
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a1169beaf0
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Update rst_on_lut_repack_dc.xml by changing the separator from , to . between pb type and pin name
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
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2023-12-04 13:34:49 -08:00 |
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Yitian4Debug
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7475a002b6
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Update repack_design_constraints.xml by changing the separater between pb type and pin name
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
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2023-12-04 13:33:55 -08:00 |
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Yitian4Debug
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5ca928efda
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Merge branch 'master' into repack_debug
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2023-12-04 13:21:10 -08:00 |
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Yitian4Debug
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37352cf25c
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Update fpga_bitstream_commands.rst with ref check marker.
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2023-12-04 11:54:49 -08:00 |
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tangxifan
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005ee39d31
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Merge pull request #1470 from lnis-uofu/dependabot/submodules/yosys-8bd681a
Bump yosys from `8614d9b` to `8bd681a`
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2023-12-04 11:52:40 -08:00 |