e10cafe0a5
Critical patch on repacking about wire LUT support.
...
Previously, the wire LUT identification is too naive and does not consider all the cases
2020-04-19 16:42:31 -06:00
2e3a811f4f
critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
2020-04-18 21:04:46 -06:00
a7d900088b
now generating simulation ini file will try to create directory first
2020-04-15 20:53:37 -06:00
72e8824a87
bug fixed on removing undriven pins (direct connection between clbs) from cb
2020-04-15 20:41:15 -06:00
2ffd174e6a
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
2020-04-15 15:48:33 -06:00
56e0d2a918
critical patch on the ccff head and tail connection in grid modules for VPR7+OpenFPGA
2020-04-13 12:58:44 -06:00
07a384e440
now use openfpga tokenizer to trim command line string in openfpga shell
2020-04-13 11:08:31 -06:00
e6c896d583
now inout must be global port and I/O port so that it will appear in the top-level module
2020-04-08 16:54:08 -06:00
b9dab2baaf
add exit codes to command execution in shell context
2020-04-08 16:18:05 -06:00
1fb37f4c71
improve directory creator to support same functionality as 'mkdir -p'
2020-04-08 12:55:09 -06:00
e31dc1f2f2
openfpga shell now support continued line charactor '\'
2020-04-07 21:27:51 -06:00
33315f0521
now openfpga shell allow empty space at beginning and end of each line in script mode
2020-04-07 20:46:45 -06:00
0b1c8ac139
bug fixed in identifying the physical interconnect for pb_graph nodes
2020-04-07 19:46:42 -06:00
62276f9e28
minor code format
2020-04-07 18:43:11 -06:00
ff7ea99381
bug fixed in register scan-chain architecture
2020-04-07 17:06:16 -06:00
2342d7cdc6
minor tweak on the scan-chain support in VPR8 as well as architecture file
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Do NOT use pack patterns for the scan-chain. It will cause searching root chain in VPR8 to fail
Actually, we do not use scan-chain in mapping designs. Disable the pack pattern has no impact
2020-04-07 17:03:44 -06:00
50bb04d496
add scan-chain test case. Debugging on the way
2020-04-07 16:50:41 -06:00
cbcd1d20d4
fixed memory leakage in pb_pin fixup
2020-04-07 16:24:04 -06:00
5a04da2082
fix memory leakage in openfpga title
2020-04-07 16:14:41 -06:00
6daee8c2c8
bug fixed in the example architecture
2020-04-07 16:03:34 -06:00
628ea3b654
improve adder chain arch XML to support sequential output for sumout
2020-04-07 15:39:37 -06:00
26d1261c1f
add test cases using shift registers
2020-04-07 15:09:10 -06:00
e61e7167b3
update circuit model names in the example tree-like MUX architecture
2020-04-07 11:27:16 -06:00
0eeb8e5317
clean up example architecture XML by removing redundant syntax
2020-04-07 11:24:42 -06:00
6d6295ef93
Add test cases about using standard cell mux2
2020-04-07 11:12:47 -06:00
d39d7a68ce
add test cases for using tree-like multiplexer
2020-04-07 10:46:49 -06:00
92a3a444f9
update VPR7 to support global I/O ports
2020-04-06 20:44:00 -06:00
13cd48c119
add support on packable/unpackable modes in VPR architecture
2020-04-06 16:07:49 -06:00
6eb125ec2a
Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML
2020-04-06 14:09:52 -06:00
3369d724e9
bug fixing in Verilog top-level testbench generation
2020-04-05 17:50:11 -06:00
decc1dc4b2
debugged global gp input/output port support
2020-04-05 17:39:30 -06:00
bcb86801fa
bug fixed in gpio naming for module manager ports
2020-04-05 17:26:44 -06:00
5f4e7dc5d4
support gpinput and gpoutput ports in module manager and circuit library
2020-04-05 16:52:21 -06:00
bc47b3ca94
update verilog module writer to the global spy ports
2020-04-05 16:04:13 -06:00
8b583b7917
debugging spy port builder in module manager
2020-04-05 16:01:25 -06:00
ca45efd13d
add testing script for the spy io
2020-04-05 15:24:40 -06:00
3b63ad6657
add test openfpga arch XML with spy pad
2020-04-05 15:23:07 -06:00
836f722f20
start supporting global output ports in module manager
2020-04-05 15:19:46 -06:00
32c74ad811
added FPGA architecture with I/Os on the left and right sides
2020-04-01 15:46:38 -06:00
63306ce3a0
add comments to explain the memory organization in the top-level module
2020-04-01 11:05:30 -06:00
07e1979498
add architecture examples on wide memory blocks (width=2). tileable routing is working
2020-03-28 15:41:26 -06:00
ff9cc50527
relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
2020-03-27 20:09:50 -06:00
e601a648cc
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
2020-03-27 19:07:34 -06:00
34a1b61ecb
add an example FPGA architecture with AIB interface at the right side of I/Os
2020-03-27 18:45:27 -06:00
4bf0a63ae6
bug fixed for multiple io types defined in FPGA architectures
2020-03-27 16:32:15 -06:00
7c9c2451f2
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
2020-03-27 16:03:42 -06:00
b09b051249
add all the test cases considering tileable, carry chain, direct connection and memory blocks
2020-03-27 13:58:35 -06:00
e47a0a4422
add through channel architecture example
2020-03-27 11:32:44 -06:00
91a618466d
bug fixing for rr_graph.clear() function
2020-03-27 10:52:48 -06:00
329b0a9cf1
add options to enable SDC constraints on zero-delay paths
2020-03-25 15:55:30 -06:00
tangxifan