tangxifan
|
90bbb50047
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[script] rename shared library name for tcl, so that it is straightforward to load in tcl
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2022-12-01 15:59:52 -08:00 |
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tangxifan
|
338e191f77
|
[script] enable swig flags when compiling vtr
|
2022-12-01 15:16:58 -08:00 |
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tangxifan
|
78d4991a4e
|
[script] add missing flags required
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2022-12-01 14:49:05 -08:00 |
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tangxifan
|
33b400de39
|
[script] compilation passed but failed when loading .so to tclsh
|
2022-12-01 13:51:50 -08:00 |
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tangxifan
|
819b716260
|
[script] debugging
|
2022-12-01 12:30:57 -08:00 |
|
tangxifan
|
2e585024f7
|
[script] debugging
|
2022-12-01 12:26:30 -08:00 |
|
tangxifan
|
48a9a97562
|
[script] enabling swig in cmake compilation
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2022-12-01 12:23:01 -08:00 |
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tangxifan
|
0574efa9b3
|
[script] reworking cmakefile for swig integration
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2022-12-01 12:06:27 -08:00 |
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tangxifan
|
10d52f1f8b
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[engine] add swig interface file
|
2022-12-01 11:54:59 -08:00 |
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tangxifan
|
74b32c3a5c
|
[script] enable shared library for openfpga
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2022-12-01 11:42:25 -08:00 |
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tangxifan
|
f1a317b384
|
[engine] format
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2022-11-24 21:04:04 -08:00 |
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tangxifan
|
24a174c7a4
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[engine] fixed syntax errors
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2022-11-23 17:06:27 -08:00 |
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tangxifan
|
07424b1e7f
|
[engine] now main() is encapuslated in a class OpenfpgaShell
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2022-11-23 16:52:22 -08:00 |
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tangxifan
|
c4de6655b6
|
[engine] bug
|
2022-10-17 15:26:21 -07:00 |
|
tangxifan
|
0f2b8da7f0
|
[engine] code format
|
2022-10-17 14:55:34 -07:00 |
|
tangxifan
|
63d8b00630
|
[engine] syntax
|
2022-10-17 14:54:18 -07:00 |
|
tangxifan
|
11624cd0c6
|
[engine] enabling new feature: pin_table_direction_convention
|
2022-10-17 14:08:21 -07:00 |
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tangxifan
|
0af6c76239
|
[engine] code format
|
2022-10-13 16:27:57 -07:00 |
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tangxifan
|
d1f3338837
|
[engine] now repacker find only routable pins when given a net to search routing traces
|
2022-10-13 16:26:45 -07:00 |
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tangxifan
|
31da9bf6ea
|
[engine] now repack can find a routing trace from the port in the same type at top-level pb_graph_node
|
2022-10-13 15:10:25 -07:00 |
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tangxifan
|
afdc071c4c
|
[engine] apply code format
|
2022-10-06 18:13:33 -07:00 |
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tangxifan
|
e2debd2dde
|
[engine] add missing header files after coding formatter sorts the include files
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2022-10-06 18:08:57 -07:00 |
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tangxifan
|
6d31b319a2
|
[engine] update source files subject to code formatting rules
|
2022-10-06 17:08:50 -07:00 |
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tangxifan
|
0d8d8446ee
|
[test] fixed a bug where OPIN for direct connection is included in GSB
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2022-09-30 15:24:51 -07:00 |
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tangxifan
|
fb2693171b
|
[engine] fixed a bug which causes errors in repacker
|
2022-09-28 16:30:11 -07:00 |
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tangxifan
|
36b3e64b35
|
[engine] now pb_fixup can also accept vtr's post-routing-clustering sync up results
|
2022-09-28 12:17:16 -07:00 |
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tangxifan
|
3285af4107
|
[engine] syntax
|
2022-09-28 11:39:37 -07:00 |
|
tangxifan
|
51f54bbf20
|
[engine] developing the steps to annotate clustering results
|
2022-09-27 16:54:48 -07:00 |
|
tangxifan
|
8272d2dcbc
|
[engine] enrich verbose output for repacker, easier to debug
|
2022-09-27 10:46:57 -07:00 |
|
tangxifan
|
e19ca1c6d1
|
[engine] fixed a bug when decoding bitstream for connnection blocks: now use incoming edges from gsb
|
2022-09-19 18:49:54 -07:00 |
|
tangxifan
|
c922259c23
|
[engine] remove warnings and update vtr
|
2022-09-19 14:53:30 -07:00 |
|
tangxifan
|
90ddd2ce32
|
[engine] now get incoming edges for IPINs only from GSB
|
2022-09-19 14:02:13 -07:00 |
|
tangxifan
|
3c6ef1925c
|
[engine] now sort ipin incoming edges
|
2022-09-19 11:00:08 -07:00 |
|
tangxifan
|
373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-16 16:47:21 -07:00 |
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tangxifan
|
f0fe781dbc
|
[engine] fixed a bug
|
2022-09-16 10:45:27 -07:00 |
|
tangxifan
|
bba5b7b070
|
[engine] syntax
|
2022-09-15 23:04:37 -07:00 |
|
tangxifan
|
cbc71c75c4
|
[engine] now io indexing follows a natural way
|
2022-09-15 23:01:35 -07:00 |
|
tangxifan
|
8378ad4bf3
|
[engine] fixed a bug on mistakenly adding I/O child modules for direct connections
|
2022-09-14 17:13:23 -07:00 |
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tangxifan
|
036933dc14
|
[engine] fixed more bugs due to the extra modules added to top-level module when using memory bank or frame-based protocols
|
2022-09-14 16:46:10 -07:00 |
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tangxifan
|
0425b00af5
|
[engine] fixed a bug for frame-based protocols
|
2022-09-14 16:41:30 -07:00 |
|
tangxifan
|
cb89488f76
|
[engine] now support a custom list for indexing I/O children in each module
|
2022-09-14 15:54:55 -07:00 |
|
tangxifan
|
eb8b7e6901
|
[engine] fixed a bug in i/o indexing
|
2022-09-14 11:30:34 -07:00 |
|
tangxifan
|
1c2192a87d
|
[engine] fixed a few bugs
|
2022-09-12 16:50:32 -07:00 |
|
tangxifan
|
2fc124e109
|
[engine] now repack has a new option "--ignore_global_nets_on_pins"
|
2022-09-12 16:18:26 -07:00 |
|
tangxifan
|
e5c7a3df9f
|
[engine] syntax
|
2022-09-07 15:51:54 -07:00 |
|
tangxifan
|
56619f9a47
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-07 15:04:05 -07:00 |
|
tangxifan
|
8d09773e65
|
[engine] remove unnecessary checks from sb mirror checker
|
2022-09-07 11:55:08 +08:00 |
|
tangxifan
|
e748c7697d
|
[engine] update code comments
|
2022-09-06 13:51:29 -07:00 |
|
tangxifan
|
eab3580f79
|
[engine] now consider circuit model rather than switchId and SegmentId when identifying GSB structure similarity
|
2022-09-06 13:40:29 -07:00 |
|
tangxifan
|
59440082ed
|
[engine] fixed some syntax errors
|
2022-09-06 11:55:40 -07:00 |