4905e694ab
[doc] typo
2024-09-18 21:59:06 -07:00
1789ce06c4
[doc] update new syntax with example
2024-09-18 17:55:05 -07:00
8a5c33b1d6
[doc] new option for perimeter cb
2024-07-08 19:01:16 -07:00
91f8bb5841
[doc] update figures for ecb
2024-07-07 13:40:01 -07:00
18e2b994ac
[doc] update syntax on clock network file
2024-06-30 22:56:31 -07:00
b491ba03b7
[doc] typo
2024-05-29 10:33:39 -07:00
391b768b3a
[doc] syntax
2024-05-21 11:14:12 -07:00
4c6b923b74
[doc] add a figure about ecb
2024-05-21 11:03:58 -07:00
5775187072
[doc] enhance connection block details and restrictions
2024-05-21 10:55:13 -07:00
be1d7517c9
[doc] rework out-of-date syntax
2024-05-17 19:25:35 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
b79703fc8b
[doc] comment on new options
2023-11-14 10:10:41 -08:00
e9673916b2
[doc] add figures for new options in tileable rr graph
2023-11-14 09:56:57 -08:00
517be141ba
[doc] format
2023-09-26 18:37:49 -07:00
b56609d210
[doc] more details
2023-09-26 15:11:26 -07:00
262e47a922
[doc] update
2023-09-25 22:34:10 -07:00
d9e3392194
[doc] add description about new option ``shrink_boundary``
2023-08-12 12:25:38 -07:00
76a553e7bc
[doc] supplementary description
2023-04-21 15:23:51 +08:00
c220438c42
[doc] adding new syntax that supports separated clocks for multi-head configuration chains
2023-04-21 15:21:34 +08:00
509f5eb6dc
[doc] add documentation about clock network description file
2023-04-20 17:06:53 +08:00
55be8f491e
fix mux syntax in circuit_model_examples
...
the documentation is inconsistent about using underscores or dashes when describing a mux. It used one-level, but multi_level. Only underscores are valid in openfpga
2023-02-10 10:22:37 -07:00
e660880419
[doc] fixed bugs on small figure sizes shown
2022-12-06 17:20:46 -08:00
0609210b39
[doc] update doc with the new xml syntax
2022-09-08 17:00:16 -07:00
781250f0bb
Fix a small typo to trigger the CI flow.
2022-03-22 16:36:45 -07:00
6ff69d26b9
[Doc] An example to the documentation about the new feature in tile_annotation
2022-03-20 13:12:13 +08:00
123bb70cb3
[Doc] More explanantion on the use of config_enable attribute for circuit ports
2022-02-23 15:53:58 -08:00
57159fc121
[Doc] Update documentation for the new syntax in configuration protocol and fabric key file format
2021-10-10 17:46:45 -07:00
40b589dc6d
[Doc] Update documentation about the clock definition for programming clocks in simulation settings
2021-10-06 13:50:33 -07:00
ff339312f6
[Doc] Update documentation about the limitations of multi-region configuration protocols
2021-10-05 11:55:10 -07:00
a01fa7c282
[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
2021-10-04 12:09:42 -07:00
b0a97a7052
[Doc] Update doc about WLR usage for QL memory bank
2021-09-27 10:24:04 -07:00
f9bceff33a
[Doc] Update documentation for the flatten BL/WL protocols
2021-09-25 20:44:45 -07:00
d9d959709c
[Doc] Add missing figures
2021-09-20 20:31:53 -07:00
3146d2484f
[Doc] Update documentation on the WLR definition for circuit model
2021-09-20 17:21:33 -07:00
73d21c9730
[Doc] Update doc about how to use the QuickLogic memory bank
2021-09-10 15:30:37 -07:00
9b40e74e25
[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
2021-05-24 15:24:50 -06:00
21a18069a1
[Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples
2021-05-24 14:50:55 -06:00
b6b98a75b8
[Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model;
2021-05-24 13:03:40 -06:00
62dc5a3856
[Doc] Update documentation about the new syntax introduced for pin binding between operating modes and physical modes
2021-04-24 16:02:24 -06:00
19b2641839
Merge branch 'master' into doc_patch
2021-03-15 11:45:32 -06:00
fb7d76545e
[Doc] Patch the schematic of LUT circuit models to be consistent with netlists
2021-03-15 11:40:09 -06:00
ff0faeb285
[Doc] Update documentation about the extended bitstream setting
2021-03-10 21:41:59 -07:00
01b9bf2a02
[Doc] Update num_region XML for config protocol
2021-02-18 21:58:30 -07:00
1c4dc9f74b
[Doc] Update documentation about the super LUT feature
2021-02-10 11:49:59 -07:00
9c5368f912
[Doc] Correct bugs in compiling latexpdf
2021-02-07 16:17:54 -07:00
9b5c64f35f
[Doc] Update documentation about disable_packing syntax
2021-02-04 16:41:24 -07:00
d53d3963d4
[Doc] Broken link fix in config protocol documentation
2021-01-26 14:05:11 -07:00
e9dc708d66
[Doc] Group file format documentation into a unified section
2021-01-19 19:44:44 -07:00
c4d3e7c50c
[Doc] Update documentation for the new XML syntax in simulation settings
2021-01-15 12:30:26 -07:00
0c808bec41
[Doc] Add clarification for defining multi-bit global tile ports
2021-01-09 20:00:16 -07:00
tangxifan
chungshien
scott-temple
taoli4rs