[doc] update

docs/source/manual/arch_lang/annotate_vpr_arch.rst

@@ -62,12 +62,25 @@ Here is an example:
 .. code-block:: xml
 
   <tile_annotations>
+    <merge_subtile_ports tile="<string>" port="<string>"/>
     <global_port name="<string>" is_clock="<bool>" clock_arch_tree_name="<string>" is_reset="<bool>" is_set="<bool>" default_val="<int>">
       <tile name="<string>" port="<string>" x="<int>" y="<int>"/>
       ...
     </global_port>
   </tile_annotations>
 
+For subtile port merge support:
+
+- ``tile="<string>"`` is the name of tile, that is defined in VPR architecture
+
+- ``port="<string>"`` is the name of a port of the tile, that is defined in VPR architecture
+
+.. note:: When defined, the given port of all the subtiles of a tile will be merged into one port. For example, a tile consists of 8 subtile ``A`` and 6 subtile ``B`` and all the subtiles have a port ``clk``, in the FPGA fabric, all the ``clk`` of the subtiles ``A`` and ``B`` will be wired to a common port ``clk`` at tile level.
+
+.. note:: When merged, the port will have a default side of ``TOP`` and index of ``0`` on all the attributes, such as width, height etc.
+
+For global port support:
+
 - ``name="<string>"`` is the port name to appear in the top-level FPGA fabric.
 
 - ``is_clock="<bool>"`` define if the global port is a clock port at the top-level FPGA fabric. An operating clock port will be driven by proper signals in auto-generated testbenches.