tangxifan
|
415fd9a8fa
|
[core] code format
|
2024-09-21 21:39:30 -07:00 |
|
tangxifan
|
9e461284d0
|
[core] standardize API for clock network intermeidate drivers
|
2024-09-21 21:38:32 -07:00 |
|
tangxifan
|
1332d426c7
|
[core] code format
|
2024-09-20 17:42:53 -07:00 |
|
tangxifan
|
965ee2190e
|
[core] support intermediate driver in clock arch
|
2024-09-20 17:42:26 -07:00 |
|
tangxifan
|
82cf7bbb8c
|
[core] Add verbose mode on find_node() for clock rr graph
|
2024-08-02 17:47:41 -07:00 |
|
tangxifan
|
ae1100ceba
|
[core] cleanup debug message
|
2024-08-02 17:05:59 -07:00 |
|
tangxifan
|
c96f899c53
|
[core] code format
|
2024-07-10 15:07:26 -07:00 |
|
tangxifan
|
a4538fb25b
|
[core] now supports to_pin in building clock network for internal driver
|
2024-07-10 15:01:18 -07:00 |
|
tangxifan
|
b2fc47a12a
|
[core] reworked i/o for clock network files
|
2024-07-10 14:34:54 -07:00 |
|
tangxifan
|
079e6f2fca
|
[core] add new syntax to support from_pin and to_pin for internal driver in clock network
|
2024-07-10 14:28:28 -07:00 |
|
tangxifan
|
0f78803759
|
[core] fixed a bug on connecting clk/rst pins from programmable network any CLB inputs
|
2024-07-09 20:47:15 -07:00 |
|
tangxifan
|
578d7c8ec0
|
[core] fixed a bug on region tap point identification
|
2024-07-01 20:58:41 -07:00 |
|
tangxifan
|
73b30841a7
|
[lib] typo
|
2024-07-01 20:56:27 -07:00 |
|
tangxifan
|
60e6e27e54
|
[core] fixed a bug on tap point identificatin
|
2024-07-01 20:45:55 -07:00 |
|
tangxifan
|
a85a6f1674
|
[core] code format
|
2024-07-01 17:57:10 -07:00 |
|
tangxifan
|
70428fd969
|
[lib] add sanity checks on global port name and clock network's global port name
|
2024-07-01 17:56:29 -07:00 |
|
tangxifan
|
df23daf026
|
[lib] sanity check on global port name and from pin name of tap points
|
2024-07-01 17:37:16 -07:00 |
|
tangxifan
|
7c487eadc9
|
[core] now clock network keep port info in a native data structure
|
2024-07-01 16:58:23 -07:00 |
|
tangxifan
|
3afb92d6a5
|
[core] code format
|
2024-06-30 22:48:15 -07:00 |
|
tangxifan
|
34fb003911
|
[core] replace width syntax with global port name
|
2024-06-29 10:46:00 -07:00 |
|
tangxifan
|
5cfd23747b
|
[core] code format
|
2024-06-28 13:47:03 -07:00 |
|
tangxifan
|
4185235a69
|
[core] now clock routing is based on tree expansion. Unused part can be disconnected
|
2024-06-27 15:02:20 -07:00 |
|
tangxifan
|
cab649893b
|
[core] update clock architecture
|
2024-06-26 18:06:39 -07:00 |
|
tangxifan
|
59be95b227
|
[core] code format
|
2024-06-26 17:58:26 -07:00 |
|
tangxifan
|
3efa97b84e
|
[core] support coordinate on clock taps
|
2024-06-26 17:40:11 -07:00 |
|
tangxifan
|
3b25e42720
|
[lib] syntax
|
2024-06-26 15:51:00 -07:00 |
|
tangxifan
|
381a8cb535
|
[lib] clock tap syntax are reworked. Support region, single, all and from/to ports
|
2024-06-26 15:41:56 -07:00 |
|
tangxifan
|
7bcbd8a88b
|
[core] code format
|
2024-06-25 11:44:50 -07:00 |
|
tangxifan
|
3b2c13402a
|
[core] syntax
|
2024-06-25 11:44:25 -07:00 |
|
tangxifan
|
31d4b4c402
|
[core] now support add internal drivers to clock tree
|
2024-06-25 11:27:22 -07:00 |
|
tangxifan
|
272d78eb43
|
[test] add a new unit test
|
2024-06-24 19:13:36 -07:00 |
|
tangxifan
|
22bee35fd1
|
[lib] mem allocate
|
2024-06-24 18:47:56 -07:00 |
|
tangxifan
|
36ef555dda
|
[lib] add example arch for clock arch with internal drivers
|
2024-06-24 18:33:47 -07:00 |
|
tangxifan
|
2eda2825b7
|
[lib] syntax
|
2024-06-24 18:28:42 -07:00 |
|
tangxifan
|
0c442f6238
|
[lib] add syntax to support internal drivers in clock network parsers
|
2024-06-24 17:54:58 -07:00 |
|
tangxifan
|
2193f108ee
|
[core] add debugging messages
|
2024-06-21 18:42:35 -07:00 |
|
tangxifan
|
ecd31955b1
|
[core] code format
|
2024-06-21 17:11:32 -07:00 |
|
tangxifan
|
3ddaefc2a2
|
[lib] syntax
|
2024-06-21 17:02:37 -07:00 |
|
tangxifan
|
1ab75cf76c
|
[lib] now link clock arch supports tap and driver default switches
|
2024-06-21 16:52:22 -07:00 |
|
tangxifan
|
9ccd14bf4d
|
[lib] now default switch of clk ntwk is split to default_tap_switch and default_driver_switch
|
2024-06-21 16:45:05 -07:00 |
|
tangxifan
|
953625b1ca
|
[core] format
|
2023-03-05 22:32:05 -08:00 |
|
tangxifan
|
de1e300ec7
|
[core] now resize rr_node for clock graph is working
|
2023-03-05 22:21:55 -08:00 |
|
tangxifan
|
81e9187aac
|
[core] debugging
|
2023-03-03 22:55:14 -08:00 |
|
tangxifan
|
4423d917fa
|
[core] debugging
|
2023-03-03 18:00:43 -08:00 |
|
tangxifan
|
29ee6e7136
|
[core] debugging
|
2023-03-03 17:33:53 -08:00 |
|
tangxifan
|
98d8c75d86
|
[code] format
|
2023-03-02 21:36:08 -08:00 |
|
tangxifan
|
02b50e3464
|
[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
|
2023-03-02 21:33:32 -08:00 |
|
tangxifan
|
46510388be
|
[core] now fabric generator can wire clock ports to routing blocks
|
2023-03-02 12:33:26 -08:00 |
|
tangxifan
|
099d9f32f4
|
[core] dev
|
2023-03-01 16:08:15 -08:00 |
|
tangxifan
|
2ff8fb8737
|
[core] wrapping up clock routing command
|
2023-02-28 16:52:54 -08:00 |