62fd0947f5
using a unified string to replace multi net names to save memory of bitstream database
2020-07-08 16:28:20 -06:00
033c92c365
precisely reserve memory for child blocks in bitstream manager
2020-07-03 22:47:21 -06:00
2783fda344
use index range instead of vector for block bitstream
2020-07-03 11:42:38 -06:00
246b4d5ac6
reserve block bits to save memory
2020-07-02 21:52:32 -06:00
dee4be96af
reserve all the input/output net storage in bitstream manager
2020-07-02 19:17:34 -06:00
675a59ecb8
Move fpga_bitstream to the libopenfpga library and add XML reader
2020-06-20 18:25:17 -06:00
5d79a3f69f
critical bug fixed when annotating the routing results.
...
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
b91c30191a
add input and output net echo in arch bitstream database
2020-06-17 00:04:55 -06:00
19c0b57df6
ignore invalid nets when decoding bitstream
2020-06-16 22:26:36 -06:00
9d0e002532
echo path in architecture bitstream database
2020-06-16 21:29:45 -06:00
65df309419
bug fixing for frame-based configuration protocol and rename some naming function to be generic
2020-06-11 19:31:10 -06:00
b80e26e711
update bitstream generator to use sorted edges
2020-03-08 15:36:47 -06:00
2c44c70557
bring pb interconnection bitstream generation online
2020-02-25 00:28:06 -07:00
712eeb1340
bring bitstream generator for routing modules online
2020-02-23 22:09:46 -07:00
tangxifan